• case-insensitive prefix search: default
  e.g., sig matches "SIGIR" as well as "signal"
• exact word search: append dollar sign ($) to word
  e.g., graph$ matches "graph", but not "graphics"
• boolean and: separate words by space
  e.g., codd model
• boolean or: connect words by pipe symbol (|)
  e.g., graph|network

Update May 7, 2017: Please note that we had to disable the phrase search operator (.) and the boolean not operator (-) due to technical problems. For the time being, phrase search queries will yield regular prefix search result, and search terms preceded by a minus will be interpreted as regular (positive) search terms.

found 50 matches

• 2013
• 
  Roberto Airoldi, Jari Nurmi:
  Design & implementation of software defined radios on a homogeneous multi-processor architecture. ISVLSI 2013: 215-216
• 
  Alexandre M. Amory, Edson I. Moreno, Fernando Moraes, Marcelo Lubaszewski:
  Determining the test sources/sinks for NoC TAMs. ISVLSI 2013: 8-13
• 
  Ankita Arora, Jude Angelo Ambrose, Jorgen Peddersen, Sri Parameswaran:
  A double-width algorithmic balancing to prevent power analysis Side Channel Attacks in AES. ISVLSI 2013: 76-83
• 
  Alexsandro Cristovão Bonatto, Altamiro Amadeu Susin:
  Memory subsystem architecture design for multimedia applications. ISVLSI 2013: 213-214
• 
  Guilherme M. Castilhos, Marcelo Mandelli, Guilherme A. Madalozzo, Fernando Moraes:
  Distributed resource management in NoC-based MPSoCs with dynamic cluster sizes. ISVLSI 2013: 153-158
• 
  Mingsong Chen, Saijie Huang, Geguang Pu, Prabhat Mishra:
  Branch-and-bound style resource constrained scheduling using efficient structure-aware pruning. ISVLSI 2013: 224-229
• 
  Yuanqing Cheng, Aida Todri-Sanial, Alberto Bosio, Luigi Dillio, Patrick Girard, Arnaud Virazel, Pascal Vivet, Marc Belleville:
  A novel method to mitigate TSV electromigration for 3D ICs. ISVLSI 2013: 121-126
• 
  Krishnaji Desai, Kenneth S. Stevens, John O'Leary:
  Symbolic verification of timed asynchronous hardware protocols. ISVLSI 2013: 147-152
• 
  Brahim Al Farisi, Elias Vansteenkiste, Karel Bruneel, Dirk Stroobandt:
  A novel tool flow for increased routing configuration similarity in multi-mode circuits. ISVLSI 2013: 96-101
• 
  Guilherme Flach, Tiago Reimann, Gracieli Posser, Marcelo O. Johann, Ricardo Reis:
  Simultaneous gate sizing and Vth assignment using Lagrangian Relaxation and delay sensitivities. ISVLSI 2013: 84-89
• 
  Kunal P. Ganeshpure, Sandip Kundu:
  On runtime task graph extraction in MPSoC. ISVLSI 2013: 171-176
• 
  Manfred Glesner, François Philipp:
  Embedded systems design for smart system integration. ISVLSI 2013: 32-33
• 
  Mei Hong, Hui Guo, Sri Parameswaran:
  Dynamic encryption key design and management for memory data encryption in embedded systems. ISVLSI 2013: 70-75
• 
  Hailong Jiao, Volkan Kursun:
  Ground gated 8T SRAM cells with enhanced read and hold data stability. ISVLSI 2013: 52-57
• 
  Marcelo O. Johann:
  Recent advances and challenges in physical design automation. ISVLSI 2013: 223
• 
  Lech Józwiak:
  HW/SW architecture co-synthesis of ASIP-based MPSoCs for highly- demanding applications. ISVLSI 2013: 145-146
• 
  Alair Dias Junior, Diógenes Cecilio da Silva Júnior:
  Using guiding heuristics to improve the dynamic checking of temporal properties in data dominated high-level designs. ISVLSI 2013: 20-25
• 
  Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal:
  STAIRoute: Global routing using monotone staircase channels. ISVLSI 2013: 90-95
• 
  Fernanda Lima Kastensmidt, Ricardo Reis, Leandro Soares Indrusiak, Gilles Sassatelli:
  Message from the general and program chairs. ISVLSI 2013
• 
  Vianney Lapotre, Purushotham Murugappa, Guy Gogniat, Amer Baghdadi, Jean-Philippe Diguet, Jean-Noel Bazin, Michael Hübner:
  A reconfigurable multi-standard ASIP-based turbo decoder for an efficient dynamic reconfiguration in a multi-ASIP context. ISVLSI 2013: 40-45
• 
  Junghee Lee, Chrysostomos Nicopoulos, Sung Joo Park, Madhavan Swaminathan, Jongman Kim:
  Do we need wide flits in Networks-on-Chip? ISVLSI 2013: 2-7
• 
  Matthew Lewandowski, Nagarajan Ranganathan, Matthew Morrison:
  Behavioral model of integrated qubit gates for quantum reversible logic design. ISVLSI 2013: 194-199
• 
  Xin Li, Wulong Liu, Haixiao Du, Yu Wang, Yuchun Ma, Huazhong Yang:
  Whitespace-aware TSV arrangement in 3D clock tree synthesis. ISVLSI 2013: 115-120
• 
  Lucas Machado, Vinícius Dal Bem, Francesc Moll, Sergio Gómez, Renato P. Ribas, André Inácio Reis:
  Logic synthesis for manufacturability considering regularity and lithography printability. ISVLSI 2013: 230-235
• 
  Lucas Machado, Mayler G. A. Martins, Vinicius Callegaro, Renato P. Ribas, André Inácio Reis:
  Iterative remapping respecting timing constraints. ISVLSI 2013: 236-241
• 
  Andrea Manuzzato, Fabio Campi, Davide Rossi, Valentino Liberali, Davide Pandini:
  Exploiting body biasing for leakage reduction: A case study. ISVLSI 2013: 133-138
• 
  Erik Jan Marinissen:
  Murphy goes 3D. ISVLSI 2013: 102
• 
  Cristina Meinhardt, Ricardo Reis:
  A yield-driven regular layout synthesis. ISVLSI 2013: 221-222
• 
  Matheus Trevisan Moreira, Ney Laert Vilar Calazans:
  Design of standard-cell libraries for asynchronous circuits with the ASCEnD flow. ISVLSI 2013: 217-218
• 
  Matthew Morrison, Nagarajan Ranganathan:
  A novel optimization method for reversible logic circuit minimization. ISVLSI 2013: 182-187

skipping 20 more matches