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2020 – today
- 2024
[e1]Iris Hui-Ru Jiang, Gracieli Posser:
Proceedings of the 2024 International Symposium on Physical Design, ISPD 2024, Taipei, Taiwan, March 12-15, 2024. ACM 2024 [contents]- 2023
- [j3]Iris Hui-Ru Jiang
, David G. Chinnery, Gracieli Posser, Jens Lienig:
Introduction to the Special Section on Advances in Physical Design Automation. ACM Trans. Design Autom. Electr. Syst. 28(5): 68:1-68:3 (2023) - 2022
- [c17]Gracieli Posser, Evangeline F. Y. Young, Stephan Held, Yih-Lang Li, David Z. Pan:
Challenges and Approaches in VLSI Routing. ISPD 2022: 185-192
2010 – 2019
- 2019
- [c16]Wen-Hao Liu, Stefanus Mantik, Wing-Kai Chow, Yixiao Ding, Amin Farshidi, Gracieli Posser:
ISPD 2019 Initial Detailed Routing Contest and Benchmark with Advanced Routing Rules. ISPD 2019: 147-151 - 2018
- [c15]Stefanus Mantik, Gracieli Posser, Wing-Kai Chow, Yixiao Ding, Wen-Hao Liu:
ISPD 2018 Initial Detailed Routing Contest and Benchmarks. ISPD 2018: 140-143 - 2016
- [j2]Gracieli Posser, Vivek Mishra, Palkesh Jain, Ricardo Reis, Sachin S. Sapatnekar:
Cell-Internal Electromigration: Analysis and Pin Placement Based Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(2): 220-231 (2016) - [c14]Alexandra L. Zimpeck, Cristina Meinhardt, Gracieli Posser, Ricardo Augusto da Luz Reis:
FinFET cells with different transistor sizing techniques against PVT variations. ISCAS 2016: 45-48 - [c13]Lucas de Paris, Gracieli Posser, Ricardo Reis:
Electromigration aware circuits by using special signal non-default routing rules. ISCAS 2016: 2795-2798 - [c12]Calebe Conceição, Gracieli Posser, Ricardo Reis:
Reducing the number of transistors with gate clustering. LASCAS 2016: 163-166 - 2015
- [c11]Alexandra L. Zimpeck, Cristina Meinhardt, Gracieli Posser, Ricardo Reis:
Process variability in FinFET standard cells with different transistor sizing techniques. ICECS 2015: 121-124 - [c10]Gracieli Posser, Vivek Mishra, Palkesh Jain, Ricardo Reis, Sachin S. Sapatnekar:
Impact on performance, power, area and wirelength using electromigration-aware cells. ICECS 2015: 129-132 - [c9]Gracieli Posser, Lucas de Paris, Vivek Mishra, Palkesh Jain, Ricardo Reis, Sachin S. Sapatnekar:
Reducing the signal Electromigration effects on different logic gates by cell layout optimization. LASCAS 2015: 1-4 - 2014
- [j1]Guilherme Flach, Tiago Reimann, Gracieli Posser, Marcelo O. Johann, Ricardo Reis:
Effective Method for Simultaneous Gate Sizing and $V$ th Assignment Using Lagrangian Relaxation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(4): 546-557 (2014) - [c8]Gracieli Posser, Vivek Mishra, Palkesh Jain, Ricardo Reis, Sachin S. Sapatnekar:
A systematic approach for analyzing and optimizing cell-internal signal electromigration. ICCAD 2014: 486-491 - [c7]Gracieli Posser, Vivek Mishra, Ricardo Augusto da Luz Reis, Sachin S. Sapatnekar:
Analyzing the electromigration effects on different metal layers and different wire lengths. ICECS 2014: 682-685 - [c6]Gracieli Posser, Jozeanne Belomo, Cristina Meinhardt, Ricardo Augusto da Luz Reis:
Perfomance Improvement with Dedicated Transistor Sizing for MOSFET and FinFET Devices. ISVLSI 2014: 418-423 - 2013
- [c5]Tiago Reimann, Gracieli Posser, Guilherme Flach, Marcelo O. Johann, Ricardo Reis:
Simultaneous gate sizing and Vt assignment using Fanin/Fanout ratio and Simulated Annealing. ISCAS 2013: 2549-2552 - [c4]Guilherme Flach, Tiago Reimann, Gracieli Posser, Marcelo O. Johann, Ricardo Reis:
Simultaneous gate sizing and Vth assignment using Lagrangian Relaxation and delay sensitivities. ISVLSI 2013: 84-89 - 2012
- [c3]Gracieli Posser, Guilherme Flach, Gustavo Wilke, Ricardo Reis:
Transistor sizing and gate sizing using geometric programming considering delay minimization. NEWCAS 2012: 85-88 - 2011
- [c2]Gracieli Posser, Guilherme Flach, Gustavo Wilke, Ricardo Reis:
Gate Sizing Minimizing Delay and Area. ISVLSI 2011: 315-316 - 2010
- [c1]Gracieli Posser, Adriel Ziesemer, Daniel Guimares Jr., Gustavo Wilke, Ricardo A. L. Reis:
A study on layout quality of automatic generated cells. ICECS 2010: 651-654
Coauthor Index
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