• case-insensitive prefix search: default
  e.g., sig matches "SIGIR" as well as "signal"
• exact word search: append dollar sign ($) to word
  e.g., graph$ matches "graph", but not "graphics"
• boolean and: separate words by space
  e.g., codd model
• boolean or: connect words by pipe symbol (|)
  e.g., graph|network

Update May 7, 2017: Please note that we had to disable the phrase search operator (.) and the boolean not operator (-) due to technical problems. For the time being, phrase search queries will yield regular prefix search result, and search terms preceded by a minus will be interpreted as regular (positive) search terms.

found 29 matches

• 2009
• 
  Sumit Ahuja, Sandeep K. Shukla:
  MCBCG: Model Checking Based Sequential Clock-Gating. HLDVT 2009: 20-25
• 
  Bijan Alizadeh, Masahiro Fujita:
  Modular arithmetic decision procedure with auto-correction mechanism. HLDVT 2009: 138-145
• 
  Gianpiero Cabodi, Leandro Dipietro, Marco Murciano, Sergio Nocco:
  Exploiting incrementality in SAT-based search for multiple equivalence-preserving transformations in combinational circuits. HLDVT 2009: 46-53
• 
  Maurizio Caramia, Stefano Di Carlo, Michele Fabiano, Paolo Prinetto:
  FLARE: A design environment for FLASH-based space applications. HLDVT 2009: 14-19
• 
  Rajat Subhra Chakraborty, Seetharam Narasimhan, Swarup Bhunia:
  Hardware Trojan: Threats and emerging solutions. HLDVT 2009: 166-171
• 
  Maheshwar Chandrasekar, Michael S. Hsiao:
  Diagnostic Test Generation for silicon diagnosis with an incremental learning framework based on search state compatibility. HLDVT 2009: 68-75
• 
  Debapriya Chatterjee, Valeria Bertacco:
  Activity-based refinement for abstraction-guided simulation. HLDVT 2009: 146-153
• 
  Huan Chen, João Marques-Silva:
  TG-PRO: A new model for SAT-based ATPG. HLDVT 2009: 76-81
• 
  Yongquan Fan, Zeljko Zilic:
  A versatile scheme for the validation, testing and debugging of High Speed Serial Interfaces. HLDVT 2009: 114-121
• 
  Hongxia Fang, Krishnendu Chakrabarty, Hideo Fujiwara:
  RTL DFT techniques to enhance defect coverage for functional test sequences. HLDVT 2009: 160-165
• 
  Kanupriya Gulati, Sunil P. Khatri:
  Fault table generation using Graphics Processing Units. HLDVT 2009: 60-67
• 
  Ziyad Hanna, Thomas F. Melham:
  A symbolic execution framework for algorithm-level modelling. HLDVT 2009: 94-99
• 
  J. Hao, Valeria Bertacco:
  PowerRanger: Assessing circuit vulnerability to power attacks using SAT-based static analysis. HLDVT 2009: 54-59
• 
  Susmit Jha, Wenchao Li, Sanjit A. Seshia:
  Localizing transient faults using dynamic bayesian networks. HLDVT 2009: 82-87
• 
  Priyank Kalla, Prabhat Mishra:
  Chairs' welcome message. HLDVT 2009: 1
• 
  Peter Lisherness, Kwang-Ting Cheng:
  An instrumented observability coverage method for system validation. HLDVT 2009: 88-93
• 
  Lingyi Liu, Shobha Vasudevan:
  STAR: Generating input vectors for design validation by static analysis of RTL. HLDVT 2009: 32-37
• 
  In-Ho Moon, Kevin Harer:
  Learning from constraints for formal property checking. HLDVT 2009: 38-45
• 
  Nicola Nicolici, Ho Fai Ko:
  Design-for-debug for post-silicon validation: Can high-level descriptions help? HLDVT 2009: 172-175
• 
  Sung-Boem Park, Subhasish Mitra:
  IFRA: Post-silicon bug localization in processors. HLDVT 2009: 154-159
• 
  Sean Safarpour, Andreas G. Veneris:
  Automated debugging with high level abstraction and refinement. HLDVT 2009: 26-31
• 
  Subodh Sharma, Ganesh Gopalakrishnan, Eric Mercer:
  Dynamic verification of Multicore Communication applications in MCAPI. HLDVT 2009: 100-105
• 
  Sunil R. Shenoy:
  Leadership Microprocessors: Validation, debug and test. HLDVT 2009: 1
• 
  Jason G. Tong, Marc Boule, Zeljko Zilic:
  Airwolf-TG: A test generator for assertion-based dynamic verification. HLDVT 2009: 106-113
• 
  Miroslav N. Velev, Ping Gao:
  Exploiting hierarchical encodings of equality to design independent strategies in parallel SMT decision procedures for a logic of equality. HLDVT 2009: 8-13
• 
  Sven Verdoolaege, Martin Palkovic, Maurice Bruynooghe, Gerda Janssens, Francky Catthoor:
  Experience with widening based equivalence checking in realistic multimedia systems. HLDVT 2009: 122-129
• 
  Bin Xue, Sandeep K. Shukla:
  Analysis of scheduled Latency insensitive systems with periodic clock calculus. HLDVT 2009: 1-7
• 
  Hao Zheng:
  A coordinated reachability analysis method for modular verification of asynchronous designs. HLDVT 2009: 130-137
• 
  IEEE International High Level Design Validation and Test Workshop, HLDVT 2009, San Francisco, CA, USA, 4-6 November 2009. IEEE Computer Society 2009, ISBN 978-1-4244-4823-4 [contents]