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2010 – 2019
- 2013
[c14]Adam B. Kinsman, Ho Fai Ko, Nicola Nicolici:
Hardware-efficient on-chip generation of time-extensive constrained-random sequences for in-system validation. DAC 2013: 121:1-121:6- 2012
- [j5]Ho Fai Ko, Nicola Nicolici:
Mapping Trigger Conditions onto Trigger Units during Post-silicon Validation and Debugging. IEEE Trans. Computers 61(11): 1563-1575 (2012) - [c13]Adam B. Kinsman, Ho Fai Ko, Nicola Nicolici:
In-system constrained-random stimuli generation for post-silicon validation. ITC 2012: 1-10 - 2011
- [j4]Ho Fai Ko, Adam B. Kinsman, Nicola Nicolici:
Design-for-Debug Architecture for Distributed Embedded Logic Analysis. IEEE Trans. Very Large Scale Integr. Syst. 19(8): 1380-1393 (2011) - 2010
- [c12]Ho Fai Ko, Nicola Nicolici:
Combining scan and trace buffers for enhancing real-time observability in post-silicon debugging. ETS 2010: 62-67 - [c11]Ho Fai Ko, Nicola Nicolici:
Automated trace signals selection using the RTL descriptions. ITC 2010: 144-153
2000 – 2009
- 2009
- [j3]Ho Fai Ko, Nicola Nicolici:
Algorithms for State Restoration and Trace-Signal Selection for Data Acquisition in Silicon Debug. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(2): 285-297 (2009) - [c10]Ho Fai Ko, Nicola Nicolici:
Resource-Efficient Programmable Trigger Units for Post-Silicon Validation. ETS 2009: 17-22 - [c9]Nicola Nicolici, Ho Fai Ko:
Design-for-debug for post-silicon validation: Can high-level descriptions help? HLDVT 2009: 172-175 - 2008
- [j2]Ho Fai Ko, Nicola Nicolici:
Scan Division Algorithm for Shift and Capture Power Reduction for At-Speed Test Using Skewed-Load Test Application Strategy. J. Electron. Test. 24(4): 393-403 (2008) - [j1]Ho Fai Ko, Nicola Nicolici:
Automated Scan Chain Division for Reducing Shift and Capture Power During Broadside At-Speed Test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(11): 2092-2097 (2008) - [c8]Ho Fai Ko, Nicola Nicolici:
On Automated Trigger Event Generation in Post-Silicon Validation. DATE 2008: 256-259 - [c7]Ho Fai Ko, Nicola Nicolici:
Automated Trace Signals Identification and State Restoration for Improving Observability in Post-Silicon Validation. DATE 2008: 1298-1303 - [c6]Ho Fai Ko, Nicola Nicolici:
A Novel Automated Scan Chain Division Method for Shift and Capture Power Reduction in Broadside At-Speed Test. ISQED 2008: 649-654 - [c5]Ho Fai Ko, Adam B. Kinsman, Nicola Nicolici:
Distributed Embedded Logic Analysis for Post-Silicon Validation of SOCs. ITC 2008: 1-10 - 2006
- [c4]Ho Fai Ko, Nicola Nicolici:
RTL Scan Design for Skewed-Load At-speed Test under Power Constraints. ICCD 2006: 237-242 - 2005
- [c3]Ho Fai Ko, Qiang Xu
, Nicola Nicolici:
Register-transfer level functional scan for hierarchical designs. ASP-DAC 2005: 1172-1175 - 2004
- [c2]Ho Fai Ko, Nicola Nicolici:
Functional Scan Chain Design at RTL for Skewed-Load Delay Fault Testing. Asian Test Symposium 2004: 454-459 - [c1]Ho Fai Ko, Nicola Nicolici:
Functional Illinois Scan Design at RTL. ICCD 2004: 78-81
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