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2010 – 2019
- 2016
[c11]Jason G. Tong, Marc Boule, Zeljko Zilic:
Accelerating assertion assessment using GPUs. HLDVT 2016: 9-16- 2013
- [j6]Jason G. Tong, Marc Boule, Zeljko Zilic:
Test compaction techniques for assertion-based test generation. ACM Trans. Design Autom. Electr. Syst. 19(1): 9:1-9:29 (2013) - [c10]Jason G. Tong, Marc Boule, Zeljko Zilic:
Efficient Data Encoding for Improving Fault Simulation Performance on GPUs. ISED 2013: 138-142 - 2010
- [j5]Jason G. Tong, Marc Boule, Zeljko Zilic:
Defining and Providing Coverage for Assertion-Based Dynamic Verification. J. Electron. Test. 26(2): 211-225 (2010) - [j4]Katell Morin-Allory, Marc Boule, Dominique Borrione, Zeljko Zilic:
Validating Assertion Language Rewrite Rules and Semantics With Automated Theorem Provers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(9): 1436-1448 (2010)
2000 – 2009
- 2009
- [c9]Yann Oddos, Katell Morin-Allory, Dominique Borrione, Marc Boule, Zeljko Zilic:
MYGEN: automata-based on-line test generator for assertion-based verification. ACM Great Lakes Symposium on VLSI 2009: 75-80 - [c8]Jason G. Tong, Marc Boule, Zeljko Zilic:
Airwolf-TG: A test generator for assertion-based dynamic verification. HLDVT 2009: 106-113 - 2008
- [j3]Marc Boule, Zeljko Zilic:
Automata-based assertion-checker synthesis of PSL properties. ACM Trans. Design Autom. Electr. Syst. 13(1): 4:1-4:21 (2008) - [c7]Katell Morin-Allory, Marc Boule, Dominique Borrione, Zeljko Zilic:
Proving and disproving assertion rewrite rules with automated theorem provers. HLDVT 2008: 56-63 - 2007
- [j2]Marc Boule, Jean-Samuel Chenard, Zeljko Zilic:
Debug enhancements in assertion-checker generation. IET Comput. Digit. Tech. 1(6): 669-677 (2007) - [c6]Marc Boule, Zeljko Zilic:
Efficient Automata-Based Assertion-Checker Synthesis of SEREs for Hardware Emulation. ASP-DAC 2007: 324-329 - [c5]Marc Boule, Jean-Samuel Chenard, Zeljko Zilic:
Assertion Checkers in Verification, Silicon Debug and In-Field Diagnosis. ISQED 2007: 613-620 - 2006
- [c4]Marc Boule, Zeljko Zilic:
Efficient Automata-Based Assertion-Checker Synthesis of PSL Properties. HLDVT 2006: 69-76 - [c3]Marc Boule, Jean-Samuel Chenard, Zeljko Zilic:
Adding Debug Enhancements to Assertion Checkers for Hardware Emulation and Silicon Debug. ICCD 2006: 294-299 - 2005
- [c2]Marc Boule, Zeljko Zilic:
Incorporating Ef.cient Assertion Checkers into Hardware Emulation. ICCD 2005: 221-228 - 2002
- [j1]Marc Boule, Zeljko Zilic:
An FPGA Move Generator for the Game of Chess. J. Int. Comput. Games Assoc. 25(2): 85-94 (2002) - [c1]Marc Boule, Zeljko Zilic:
An FPGA based move generator for the game of chess. CICC 2002: 71-74
Coauthor Index
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