- Daijoon Hyun
, Younggwang Jung, Youngsoo Shin:
Decap Insertion With Local Cell Relocation Minimizing IR-Drop Violations and Routing DRVs. IEEE Trans. Very Large Scale Integr. Syst. 32(5): 823-834 (2024) - Kashif Inayat, Inayat Ullah, Jaeyong Chung:
Factored Systolic Arrays Based on Radix-8 Multiplication for Machine Learning Acceleration. IEEE Trans. Very Large Scale Integr. Syst. 32(7): 1205-1215 (2024) - Behdad Jamadi, Shiuh-Hua Wood Chiang, Armin Tajalli:
Trade-Offs in Design of Wide-Band Inverter-Based Amplifiers. IEEE Trans. Very Large Scale Integr. Syst. 32(7): 1364-1368 (2024) - Meenali Janveja, Rushik Parmar, Srichandan Dash, Jan Pidanic, Gaurav Trivedi:
A Low-Power Co-Processor to Predict Ventricular Arrhythmia for Wearable Healthcare Devices. IEEE Trans. Very Large Scale Integr. Syst. 32(9): 1672-1683 (2024) - Zuzana Jelcicová, Evangelia Kasapaki, Oskar Andersson, Jens Sparsø:
PeakEngine: A Deterministic On-the-Fly Pruning Neural Network Accelerator for Hearing Instruments. IEEE Trans. Very Large Scale Integr. Syst. 32(1): 150-163 (2024) - Musha Ji'e, Hongxin Peng, Shukai Duan, Lidan Wang, Fengqing Zhang, Dengwei Yan:
Design and FPGA Implementation of Grid-Scroll Hamiltonian Conservative Chaotic Flows With a Line Equilibrium. IEEE Trans. Very Large Scale Integr. Syst. 32(4): 658-668 (2024) - Oliver Lexter July A. Jose, Venkata Naveen Kolakaluri, Ralph Gerard B. Sangalang, Lean Karlo S. Tolentino, Chua-Chin Wang:
A 6.25-MHz 3.4-mW Single Clock DPWM Technique Using Matrix Shift Array. IEEE Trans. Very Large Scale Integr. Syst. 32(5): 972-976 (2024) - Ziyang Kang, Jingwei Zhu, Xun Xiao, Shiming Li, Lei Wang, De Ma, Gang Pan:
LSM-Based Hotspot Prediction and Hotspot-Aware Routing in NoC-Based Neuromorphic Processor. IEEE Trans. Very Large Scale Integr. Syst. 32(7): 1239-1252 (2024) - Sunwoong Kim, Cameron James Norris, James I. Oelund, Rob A. Rutenbar:
Area-Efficient Iterative Logarithmic Approximate Multipliers for IEEE 754 and Posit Numbers. IEEE Trans. Very Large Scale Integr. Syst. 32(3): 455-467 (2024) - Jinwoo Kim, Lingjun Zhu, Hakki Mert Torun, Madhavan Swaminathan, Sung Kyu Lim:
A PPA Study for Heterogeneous 3-D IC Options: Monolithic, Hybrid Bonding, and Microbumping. IEEE Trans. Very Large Scale Integr. Syst. 32(3): 401-412 (2024) - Shin-Chi Lai, Szu-Ting Wang, Yi-Chang Zhu, Ying-Hsiu Hung, Jeng-Dao Lee, Wei-Da Chen:
High-Accuracy and Low-Multiplication Recursive Discrete Cosine Transform Algorithm Design and Its Realization in Mel-Scale Frequency Cepstral Coefficients. IEEE Trans. Very Large Scale Integr. Syst. 32(11): 2139-2143 (2024) - Yi-Hao Lan, Shen-Iuan Liu:
A 0.079-pJ/b/dB 32-Gb/s 2× Half-Baud-Rate CDR Circuit With Frequency Detector. IEEE Trans. Very Large Scale Integr. Syst. 32(4): 704-713 (2024) - Yi-Hao Lan, Shen-Iuan Liu:
A 36-Gb/s 2× Half-Baud-Rate Adaptive Receiver in 28-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 32(7): 1263-1272 (2024) - Christian Lanius, Tobias Gemmeke:
Fully Digital, Standard-Cell-Based Multifunction Compute-in-Memory Arrays for Genome Sequencing. IEEE Trans. Very Large Scale Integr. Syst. 32(1): 30-41 (2024) - Hayoung Lee, Sooryeong Lee, Sungho Kang:
RA-Aware Fail Data Collection Architecture for Cost Reduction. IEEE Trans. Very Large Scale Integr. Syst. 32(6): 1136-1149 (2024) - Hayoung Lee, Jongho Park, Sungho Kang:
An Area-Efficient Systolic Array Redundancy Architecture for Reliable AI Accelerator. IEEE Trans. Very Large Scale Integr. Syst. 32(10): 1950-1954 (2024) - Hongge Li, Yuhao Chen:
Hybrid Stochastic Number and Its Neural Network Computation. IEEE Trans. Very Large Scale Integr. Syst. 32(3): 432-441 (2024) - Xiao Li, Lin Chen, Shixi Chen, Fan Jiang, Chengeng Li, Wei Zhang, Jiang Xu:
Deep Reinforcement Learning-Based Power Management for Chiplet-Based Multicore Systems. IEEE Trans. Very Large Scale Integr. Syst. 32(9): 1726-1739 (2024) - Dengquan Li, Tian Feng, Jiale Ding, Yi Shen, Shubin Liu, Zhangming Zhu:
A Wideband Input Buffer Based on Cascade Complementary Source Follower. IEEE Trans. Very Large Scale Integr. Syst. 32(5): 962-966 (2024) - Fan Li, Qi Yun Guan, Wen Bin Ye:
A Hardware and Software Co-Design for Energy-Efficient Neural Network Accelerator With Multiplication-Less Folded-Accumulative PE for Radar-Based Hand Gesture Recognition. IEEE Trans. Very Large Scale Integr. Syst. 32(10): 1964-1968 (2024) - Chao Li, Chen Sun, Jianyi Yang, Kai Ni, Xiao Gong, Cheng Zhuo, Xunzhao Yin:
Multibit Content Addressable Memory Design and Optimization Based on 3-D nand-Compatible IGZO Flash. IEEE Trans. Very Large Scale Integr. Syst. 32(8): 1380-1388 (2024) - Enlai Li, Sharad Sinha, Wei Zhang:
Unveiling the Advantages of Full Coherency Architecture for FPSoC Systems. IEEE Trans. Very Large Scale Integr. Syst. 32(8): 1549-1553 (2024) - Yuyang Li, Vijay Shankaran Vivekanand, Rajkumar Kubendran, Inhee Lee:
Dynamic Neural Fields Accelerator Design for a Millimeter-Scale Tracking System. IEEE Trans. Very Large Scale Integr. Syst. 32(10): 1940-1944 (2024) - Dongrui Li, Ming Ming Wong, Yi Sheng Chong, Jun Zhou, Mohit Upadhyay, Ananta Narayanan Balaji, Aarthy Mani, Weng-Fai Wong, Li-Shiuan Peh, Anh Tuan Do, Bo Wang:
1.63 pJ/SOP Neuromorphic Processor With Integrated Partial Sum Routers for In-Network Computing. IEEE Trans. Very Large Scale Integr. Syst. 32(11): 2085-2092 (2024) - Zeju Li, Qinfan Wang, Zihan Zou, Qiao Shen, Na Xie, Hao Cai, Hao Zhang, Bo Liu:
Layer-Sensitive Neural Processing Architecture for Error-Tolerant Applications. IEEE Trans. Very Large Scale Integr. Syst. 32(5): 797-809 (2024) - Bin Li, Yunfei Yan, Yuanxin Wei, Heru Han:
Scalable and Parallel Optimization of the Number Theoretic Transform Based on FPGA. IEEE Trans. Very Large Scale Integr. Syst. 32(2): 291-304 (2024) - Jia-Zhao Lin, Po-Ta Chen, Hung-Yuan Chin, Pei-Yun Tsai, Sz-Yuan Lee:
Design and Implementation of a Real-Time Imaging Processor for Spaceborne Synthetic Aperture Radar With Configurability. IEEE Trans. Very Large Scale Integr. Syst. 32(4): 669-681 (2024) - Yu-Cheng Lin, Ren-Hao Chiou, Chia-Hsiang Yang:
A High-Throughput Constructive Interference Precoder for 16 × MU-MIMO Systems. IEEE Trans. Very Large Scale Integr. Syst. 32(10): 1878-1888 (2024) - Jhe-En Lin, Yi-Hao Lan, Shen-Iuan Liu:
A 40-Gb/s PAM-3 Receiver With Modified Summer-Merged Slicers and PRTS Checker. IEEE Trans. Very Large Scale Integr. Syst. 32(8): 1512-1522 (2024) - Xian Lin, Heming Liu, Xin Zheng, Huaien Gao, Shuting Cai, Xiaoming Xiong:
FPUx: High-Performance Floating-Point Support for Cost-Constrained RISC-V Cores. IEEE Trans. Very Large Scale Integr. Syst. 32(10): 1945-1949 (2024)
