- Dragan Lambic
, Aleksandar Jankovic, Musheer Ahmad:
Security Analysis of the Efficient Chaos Pseudo-random Number Generator Applied to Video Encryption. J. Electron. Test. 34(6): 709-715 (2018) - Marcos T. Leipnitz, Gabriel L. Nazar:
Fault Tolerance Mechanisms for FPGA-Based Regular Expression Matching. J. Electron. Test. 34(4): 487-506 (2018) - Shyue-Kung Lu, Hao-Cheng Jheng, Hao-Wei Lin, Masaki Hashizume:
Address Remapping Techniques for Enhancing Fabrication Yield of Embedded Memories. J. Electron. Test. 34(4): 435-446 (2018) - Shyue-Kung Lu, Shang-Xiu Zhong, Masaki Hashizume:
Fault Leveling Techniques for Yield and Reliability Enhancement of NAND Flash Memories. J. Electron. Test. 34(5): 559-570 (2018) - Hani Malloug, Manuel J. Barragán, Salvador Mir:
Practical Harmonic Cancellation Techniques for the On-Chip Implementation of Sinusoidal Signal Generators for Mixed-Signal BIST Applications. J. Electron. Test. 34(3): 263-279 (2018) - Eman El Mandouh, Amr G. Wassal:
Application of Machine Learning Techniques in Post-Silicon Debugging and Bug Localization. J. Electron. Test. 34(2): 163-181 (2018) - Yassine Naija, Vincent Beroulle, Mohsen Machhout:
Security Enhancements of a Mutual Authentication Protocol Used in a HF Full-Fledged RFID Tag. J. Electron. Test. 34(3): 291-304 (2018) - Stelios N. Neophytou, Maria K. Michael:
Path Representation in Circuit Netlists Using Linear-Sized ZDDs with Optimal Variable Ordering. J. Electron. Test. 34(6): 667-683 (2018) - M. A. Nourian, Mahdi Fazeli, David Hély:
Hardware Trojan Detection Using an Advised Genetic Algorithm Based Logic Testing. J. Electron. Test. 34(4): 461-470 (2018) - Muhammad Osama, Lamya Gaber, Aziza I. Hussein, Hanafy Mahmoud:
An Efficient SAT-Based Test Generation Algorithm with GPU Accelerator. J. Electron. Test. 34(5): 511-527 (2018) - J. Qing, Y. Zeng, Xiaojin Li, P. J. Zhang, Yabin Sun, Yanling Shi:
Analytical Low Frequency NBTI Compact Modeling with H2 Locking and Electron Fast Capture and Emission. J. Electron. Test. 34(5): 599-605 (2018) - Vijaypal Singh Rathor, Bharat Garg, G. K. Sharma:
New Lightweight Architectures for Secure FSM Design to Thwart Fault Injection and Trojan Attacks. J. Electron. Test. 34(6): 697-708 (2018) - Mostafa E. Salehi, Ali Azarpeyvand, Armin Hajaboutalebi Aboutalebi:
Vulnerability Analysis of Adder Architectures Considering Design and Synthesis Constraints. J. Electron. Test. 34(1): 7-14 (2018) - Peter Sarson, Tomonori Yanagida, Kosuke Machida:
Measuring Group Delay of Frequency Downconverter Devices Using a Chirped RF Modulated Signal. J. Electron. Test. 34(3): 233-253 (2018) - Peter Sarson, Tomonori Yanagida, Shohei Shibuya, Kosuke Machida, Haruo Kobayashi:
A Distortion Shaping Technique to Equalize Intermodulation Distortion Performance of Interpolating Arbitrary Waveform Generators in Automated Test Equipment. J. Electron. Test. 34(3): 215-232 (2018) - Toral Shah, Anzhela Yu. Matrosova, Masahiro Fujita, Virendra Singh:
Multiple Stuck-at Fault Testability Analysis of ROBDD Based Combinational Circuit Design. J. Electron. Test. 34(1): 53-65 (2018) - Pralhadrao V. Shantagiri, Rohit Kapur:
Handling Unknown with Blend of Scan and Scan Compression. J. Electron. Test. 34(2): 135-146 (2018) - Congyin Shi, Sanghoon Lee, Sergio Soto Aguilar, Edgar Sánchez-Sinencio:
A Time-Domain Digital-Intensive Built-In Tester for Analog Circuits. J. Electron. Test. 34(3): 313-320 (2018) - Felipe G. A. e Silva, Jardel Silveira, Jarbas Silveira, César A. M. Marcon, Fabian Vargas, Otávio Alcântara de Lima Jr.:
An Extensible Code for Correcting Multiple Cell Upset in Memory Arrays. J. Electron. Test. 34(4): 417-433 (2018) - Michael A. Skitsas, Chrysostomos A. Nicopoulos, Maria K. Michael:
Exploring System Availability During Software-Based Self-Testing of Multi-core CPUs. J. Electron. Test. 34(1): 67-81 (2018) - Mengbo Sun, Hongjun Lv, Yongqiang Zhang, Guangjun Xie:
The Fundamental Primitives with Fault-Tolerance in Quantum-Dot Cellular Automata. J. Electron. Test. 34(2): 109-122 (2018) - Vasudevan Madampu Suryasarman, Santosh Biswas, Aryabartta Sahu:
Automation of Test Program Synthesis for Processor Post-silicon Validation. J. Electron. Test. 34(1): 83-103 (2018) - Naoki Terao, Toru Nakura, Masahiro Ishida, Rimon Ikeno, Takashi Kusaka, Tetsuya Iizuka, Kunihiro Asada:
Digitally-Controlled Compensation Current Injection to ATE Power Supply for Emulation of Customer Environment. J. Electron. Test. 34(2): 147-161 (2018) - Pablo Ilha Vaz, Thiago Hanna Both, Fábio Fedrizzi Vidor, Raphael Martins Brum, Gilson I. Wirth:
Design Flow Methodology for Radiation Hardened by Design CMOS Enclosed-Layout-Transistor-Based Standard-Cell Library. J. Electron. Test. 34(6): 735-747 (2018) - New Editor - 2018. J. Electron. Test. 34(1): 3 (2018)
- Test Technology Newsletter. J. Electron. Test. 34(1): 5-6 (2018)
- Test Technology Newsletter. J. Electron. Test. 34(2): 107-108 (2018)
- Test Technology Newsletter. J. Electron. Test. 34(3): 211-212 (2018)
- Test Technology Newsletter. J. Electron. Test. 34(4): 373-374 (2018)
- Test Technology Newsletter. J. Electron. Test. 34(5): 509-510 (2018)
