- Scott Davidson:
Fault Simulation at the Architectural Level. ITC 1984: 669-679 - John R. Day:
A Fault-Driven, Comprehensive Redundancy Algorithm for Repair of Dynamic RAMs. ITC 1984: 287-293 - Stephen P. Denker, Judy Cobb:
Automatic Visual Testing: A New, Comprehensive Element of Cost-Effective PCB Testing Strategies. ITC 1984: 558-563 - Bulent I. Dervisoglu:
On Coosing a Hardware Descriptive Language for Digital Systems Testing/Verification. ITC 1984: 184-187 - Yacoub M. El-Ziq, Hamid H. Butt:
Impact of Mixed-Mode Self Test on Life Cycle Cost of VLSI Based Design. ITC 1984: 338-349 - Gerard FitzPatrick, David F. Peach, Richard P. Cushman:
An Automated Test of a Disk Product Power System Independent of the Primary Function of the Machine. ITC 1984: 513-517 - M. Gerner, Hans Nertinger:
Scan Path in CMOS Semicustom LSI Chips ? ITC 1984: 834-841 - David Giles, Gregory A. Maston:
Device Models : A New Methodology for a Perennial Problem. ITC 1984: 768-772 - Prabhakar Goel:
Testability Analysis will not Replace Fault Simulation. ITC 1984: 722-724 - Y. Goto, K. Ozaki, T. Ishizuka, A. Ito, Y. Furukawa, T. Inagaki:
Electron Beam Prober for LSI Testing with 100ps Time Resolution. ITC 1984: 543-549 - Frederick G. Hall, Robert G. Hillman, John M. Bednarczyk:
"Instant On" Semiconductor Memories: Reality or Myth. ITC 1984: 258-262 - Peter Hansen:
A Multimode Programming Strategy for VLSI Boards. ITC 1984: 737-742 - Syed Zahoor Hassan, Edward J. McCluskey:
Pseudo-Exhaustive Testing of Sequential Machines Using Signature Analysis. ITC 1984: 320-326 - James T. Healy:
An Information Processing Software System for ATE. ITC 1984: 497-505 - Brian J. Heard, Ramu N. Sheshadri, Ronald B. David, Arvid G. Sammuli:
Automatic Test Pattern Generation for Asynchronous Networks. ITC 1984: 63-69 - Francois J. Henley:
An Automated Laser Prober to Determine VLSI Internal Node Logic States. ITC 1984: 536-542 - G. Heretz, L. T. Matlock:
A Real-time Executive for a Distributed Processing System. ITC 1984: 627-629 - Anthony P. van den Heuvel, Noshir F. Khory:
A Rational Basis for Setting Burn-In Yield Criteria. ITC 1984: 524-530 - Edward S. Hirgelt:
Knowledge Representation in an In-Circuit Test Program Generator. ITC 1984: 773-777 - Eugene R. Hnatek:
Thoughts on VLSI Burn-in. ITC 1984: 531-535 - Mark S. Hoffman, Joseph F. Wrinn:
Channel Card Architecture for Multimode Board Test Systems. ITC 1984: 589-597 - Alexander Holland:
High Resolution, High Linearity Interpolating A/D Converter. ITC 1984: 96-104 - Joseph L. A. Hughes, Edward J. McCluskey:
An Analysis of the Multiple Fault Detection Capabilities of Single Stuck-at Fault Test Sets. ITC 1984: 52-58 - Axel Hunger, Axel Gärtner:
Functional Characterization of Microprocessors. ITC 1984: 794-803 - Philip C. Jackson, Gregory de Mare, Albert Esser:
Compaction Technique Universal Pin Electronics. ITC 1984: 471-481 - Robert G. Jacobson:
PAL and Logic Array In-Circuit Testing Considerations. ITC 1984: 743-746 - Gordon H. Bowers Jr., Bruce G. Pratt:
"Low Cost Testers" : Are They Really Low Cost ? ITC 1984: 40-51 - Ramin Khorram:
Functional Test Pattern Generation for Integrated Circuits. ITC 1984: 246-249 - Charles R. Kime, H. H. Kwan, J. K. Lemke, Gerald B. Williams:
A Built-In Test Methodology for VLSI Data Paths. ITC 1984: 327-337 - Terence King:
Advanced Test System Software Architecture Blends High Speed with User Friendliness. ITC 1984: 606-613
