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ORCIDYacoub M. El-Ziq
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1990 – 1999
- 1992
[c10]Wei-Cheng Her, Lin-Ming Jin, Yacoub M. El-Ziq:
An ATPG Driver Selection Algorithm for Interconnect Test with Boundary Scan. ITC 1992: 382-388- 1990
- [j3]Youngju Won, Sartaj Sahni, Yacoub M. El-Ziq:
A Hardware Accelerator for Maze Routing. IEEE Trans. Computers 39(1): 141-145 (1990)
1980 – 1989
- 1987
- [c9]Youngju Won, Sartaj Sahni, Yacoub M. El-Ziq:
A Hardware Accelerator for Maze Routing. DAC 1987: 800-806 - 1984
- [c8]Yacoub M. El-Ziq, Hamid H. Butt:
Impact of Mixed-Mode Self Test on Life Cycle Cost of VLSI Based Design. ITC 1984: 338-349 - 1983
- [c7]Yacoub M. El-Ziq, Hamid H. Butt:
A Mixed-Mode Built-In Self-Test Technique Using Scan Path and Signature Analysis. ITC 1983: 269-274 - 1982
- [j2]Yacoub M. El-Ziq, Stephen Y. H. Su:
Fault Diagnosis of MOS Combinational Networks. IEEE Trans. Computers 31(2): 129-139 (1982) - 1981
- [c6]Yacoub M. El-Ziq:
Automatic test generation for stuck-open faults in CMOS VLSI. DAC 1981: 347-354 - [c5]Yacoub M. El-Ziq, Richard J. Cloutier:
Functional-Level Test Generation for Stuck-Open Faults in CMOS VLSI. ITC 1981: 536-546 - 1980
- [c4]Yacoub M. El-Ziq:
A new test pattern generation system. DAC 1980: 62-68
1970 – 1979
- 1979
- [c3]Yacoub M. El-Ziq:
Testing of MOS combinational networks a procedure for efficient fault simulation and test generation. DAC 1979: 162-170 - 1978
- [j1]Yacoub M. El-Ziq, Stephen Y. H. Su:
Computer-Aided Logic Design of Two-Level MOS Combinational Networks with Statistical Results. IEEE Trans. Computers 27(10): 911-923 (1978) - [c2]Yacoub M. El-Ziq:
Logic design automation of MOS combinational networks with fan-in, fan-out constraints. DAC 1978: 240-249 - 1977
- [c1]Yacoub M. El-Ziq, Stephen Y. H. Su:
Logic design automation of diagnosable MOS combinational logic networks. DAC 1977: 205-215
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