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Journal Articles
- 2010
[j41]Kostas Siozios
, Dimitrios Soudris, Antonios Thanailakis:
A Novel Allocation Methodology for Partial and Dynamic Bitstream Generation for FPGA Architectures. J. Circuits Syst. Comput. 19(3): 701-717 (2010)- 2008
- [j40]Kostas Siozios, Dimitrios Soudris, Antonios Thanailakis:
Designing a General-Purpose Interconnection Architecture for Field Programmable Gate Arrays. J. Low Power Electron. 4(1): 34-47 (2008) - [j39]Minas Dasygenis, K. Mitroglou, Dimitrios Soudris, Adonios Thanailakis:
A Full-Adder-Based Methodology for the Design of Scaling Operation in Residue Number System. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(2): 546-558 (2008) - [j38]Vasilios A. Mardiris, Georgios Ch. Sirakoulis, Ch. Mizas, Ioannis Karafyllidis, Adonios Thanailakis:
A CAD System for Modeling and Simulation of Computer Networks Using Cellular Automata. IEEE Trans. Syst. Man Cybern. Part C 38(2): 253-264 (2008) - 2007
- [j37]Marios Kesoulis, Dimitrios Soudris, Christos S. Koukourlis, Adonios Thanailakis:
Systematic methodology for designing low power direct digital frequency synthesisers. IET Circuits Devices Syst. 1(4): 293-304 (2007) - [j36]Konstantinos Tatas, George Koutroumpezis, Dimitrios Soudris, Adonios Thanailakis:
Architecture design of a coarse-grain reconfigurable multiply-accumulate unit for data-intensive applications. Integr. 40(2): 74-93 (2007) - [j35]Stylianos Mamagkakis, Alexandros Bartzas, Georgios Pouiklis, David Atienza, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis:
Systematic methodology for exploration of performance - Energy trade-offs in network applications using Dynamic Data Type refinement. J. Syst. Archit. 53(7): 417-436 (2007) - 2006
- [j34]Stylianos Mamagkakis, Christos Baloukas, David Atienza, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis:
Reducing memory fragmentation in network applications with dynamic memory allocators optimized for performance. Comput. Commun. 29(13-14): 2612-2620 (2006) - [j33]Minas Dasygenis, Erik Brockmeyer, Bart Durinck, Francky Catthoor, Dimitrios Soudris, Adonios Thanailakis:
A combined DMA and application-specific prefetching approach for tackling the memory latency bottleneck. IEEE Trans. Very Large Scale Integr. Syst. 14(3): 279-291 (2006) - [j32]Nikolas Kroupis, Nikolaos D. Zervas, Minas Dasygenis, Konstantinos Tatas, Antonios Argyriou, Dimitrios Soudris, Antonios Thanailakis:
Behavioral-Level Performance and Power Exploration of Data-Intensive Applications Mapped on Programmable Processors. J. VLSI Signal Process. 44(1-2): 153-171 (2006) - 2005
- [j31]Georgios Ch. Sirakoulis, V. Raptis, Ioannis Karafyllidis, Philippos Tsalides, Adonios Thanailakis:
A fault-tolerant message passing algorithm and its hardware implementation. Adv. Eng. Softw. 36(3): 159-171 (2005) - [j30]Georgios Ch. Sirakoulis, Ioannis Karafyllidis, Adonios Thanailakis:
A cellular automaton for the propagation of circular fronts and its applications. Eng. Appl. Artif. Intell. 18(6): 731-744 (2005) - [j29]Kostas Siozios, George Koutroumpezis, Konstantinos Tatas, Nikolaos Vassiliadis, Vasilios Kalenteridis, Haroula Pournara, Ilias Pappas, Dimitrios Soudris, Antonios Thanailakis, Spiridon Nikolaidis, Stilianos Siskos:
A Novel FPGA Architecture and an Integrated Framework of CAD Tools for Implementing Applications. IEICE Trans. Inf. Syst. 88-D(7): 1369-1380 (2005) - [j28]Konstantinos Tatas, Dimitrios Soudris, D. Siomos, Adonios Thanailakis:
A Novel Division Algorithm and Architectures for Parallel and Sequential Processing. J. Circuits Syst. Comput. 14(2): 281-296 (2005) - [j27]Konstantinos Tatas, Dimitrios Soudris, Adonios Thanailakis:
Memory power optimization of hardware implementations of multimedia applications onto FPGA platforms. J. Embed. Comput. 1(3): 353-362 (2005) - [j26]N. A. Hastas, N. Archontas, C. A. Dimitriadis, G. Kamarinos, T. Nikolaidis, N. Georgoulas, Adonios Thanailakis:
Substrate current and degradation of n-channel polycrystalline silicon thin-film transistors. Microelectron. Reliab. 45(2): 341-348 (2005) - 2004
- [j25]Ioannis Tsimperidis, Ioannis Karafyllidis, Antonios Thanailakis:
Design and simulation of a nanoelectronic single-electron universal Control-Control-Not gate. Microelectron. J. 35(5): 471-478 (2004) - 2003
- [j24]Georgios Ch. Sirakoulis, Ioannis Karafyllidis, Ch. Mizas, Vasilios A. Mardiris, Adonios Thanailakis, Philippos Tsalides:
A cellular automaton model for the study of DNA sequence evolution. Comput. Biol. Medicine 33(5): 439-453 (2003) - [j23]Georgios Ch. Sirakoulis, Ioannis Karafyllidis, Adonios Thanailakis:
A CAD system for the construction and VLSI implementation of Cellular Automata algorithms using VHDL. Microprocess. Microsystems 27(8): 381-396 (2003) - [j22]Konstantinos Tatas, Minas Dasygenis, Nikolas Kroupis, Antonios Argyriou, Dimitrios Soudris, Antonios Thanailakis:
Data memory power optimization and performance exploration of embedded systems for implementing motion estimation algorithms. Real Time Imaging 9(6): 371-386 (2003) - 2002
- [j21]Georgios Ch. Sirakoulis, Ioannis Karafyllidis, Adonios Thanailakis:
A cellular automaton methodology for the simulation of integrated circuit fabrication processes. Future Gener. Comput. Syst. 18(5): 639-657 (2002) - [j20]S. Theoharis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis, Adonios Thanailakis:
A fast and accurate delay dependent method for switching estimation of large combinational circuits. J. Syst. Archit. 48(4-5): 113-124 (2002) - 1998
- [j19]Ioannis Karafyllidis, Ioannis Andreadis, Philippos G. Tsalides, Adonios Thanailakis:
Non-linear Hybrid Cellular Automata as Pseudorandom Pattern Generators for VLSI Systems. VLSI Design 7(2): 177-189 (1998) - 1997
- [j18]Panagiotis Tzionas, Adonios Thanailakis, Philippos G. Tsalides:
An efficient algorithm for the largest empty figure problem based on a 2D cellular automaton architecture. Image Vis. Comput. 15(1): 35-45 (1997) - [j17]Ioannis Karafyllidis, A. Ioannidis, Adonios Thanailakis, Philippos Tsalides:
Geometrical Shape Recognition Using a Cellular Automaton Architecture and its VLSI Implementation. Real Time Imaging 3(4): 243-254 (1997) - [j16]Panagiotis Tzionas, Adonios Thanailakis, Philippos G. Tsalides:
Collision-free path planning for a diamond-shaped robot using two-dimensional cellular automata. IEEE Trans. Robotics Autom. 13(2): 237-250 (1997) - 1996
- [j15]Panagiotis Tzionas, Antonios Thanailakis, Philippos Tsalides:
A hybrid cellular automaton/neural network classifier for multi-valued patterns and its VLSI implementation. Integr. 20(2): 211-237 (1996) - [j14]Ioannis Andreadis, Ioannis Karafyllidis, Panagiotis Tzionas, Adonios Thanailakis, Philippos Tsalides:
A new hardware module for automated visual inspection based on a cellular automaton architecture. J. Intell. Robotic Syst. 16(1): 89-102 (1996) - [j13]Ioannis Karafyllidis, Ioannis Andreadis, Panagiotis Tzionas, Philippos G. Tsalides, Adonios Thanailakis:
A cellular automaton for the determination of the mean velocity of moving objects and its VLSI implementation. Pattern Recognit. 29(4): 689-699 (1996) - 1995
- [j12]Panagiotis Tzionas, Philippos G. Tsalides, Adonios Thanailakis:
A Parallel Skeletonization Algorithm Based on Two-Dimensional Cellular Automata and its VLSI Implementation. Real Time Imaging 1(2): 105-117 (1995) - 1994
- [j11]E. D. Adamides, Philippos G. Tsalides, Adonios Thanailakis:
Bit-serial VLSI sorter with high reliability specifications. Microprocess. Microprogramming 40(8): 523-536 (1994) - [j10]Panagiotis Tzionas, Philippos Tsalides, Adonios Thanailakis:
A modified discrete Fourier-cosine transform algorithm and its VLSI implementation. Microprocess. Microsystems 18(6): 343-350 (1994) - [j9]Panagiotis Tzionas, Philippos G. Tsalides, Adonios Thanailakis:
A new, cellular automaton-based, nearest neighbor pattern classifier and its VLSI implementation. IEEE Trans. Very Large Scale Integr. Syst. 2(3): 343-353 (1994) - 1993
- [j8]Panagiotis Tzionas, Philippos Tsalides, Antonios Thanailakis:
2-Dimensional minimum cost path planning using a cellular automaton architecture. Integr. 16(2): 179-194 (1993) - 1992
- [j7]Emmanuel D. Adamides, Philippos Tsalides, Adonios Thanailakis:
Hierarchical Cellular Graph Automata as a Novel Architecture for Computer-Supported Cooperative Work. Comput. J. 35(Additional-Papers): A317-A328 (1992) - [j6]Philippos Tsalides, Adonios Thanailakis, Nikos Pitsianis, Georgios L. Bleris:
Two-Dimensional Cellular Automata: Properties and Applications of a New VLSI Architecture. Comput. J. 35(Additional-Papers): A377-A386 (1992) - [j5]E. D. Adamides, Philippos Tsalides, Adonios Thanailakis:
Hierarchical Cellular Automata structures. Parallel Comput. 18(5): 517-524 (1992) - 1989
- [j4]Nikos Pitsianis, Georgios L. Bleris, Philippos Tsalides, Adonios Thanailakis, Howard C. Card:
Algebraic Theory of Bounded One-dimensional Cellular Automata. Complex Syst. 3(2) (1989) - [j3]E. D. Adamides, Philippos Tsalides, Adonios Thanailakis:
Synchronization of D. Parkinsonasynchronous concurrent processes using cellular automata. Parallel Comput. 11(2): 163-169 (1989) - 1986
- [j2]Howard C. Card, Adonios Thanailakis, Werner Pries, Robert D. McLeod:
Analysis of Bounded Linear Cellular Automata Based on a Method of Image Charges. J. Comput. Syst. Sci. 33(3): 473-480 (1986) - [j1]Werner Pries, Adonios Thanailakis, Howard C. Card:
Group Properties of Cellular Automata and VLSI Applications. IEEE Trans. Computers 35(12): 1013-1024 (1986)
Conference and Workshop Papers
- 2007
- [c45]Kostas Siozios, Stelios Mamagkakis, Dimitrios Soudris, Antonios Thanailakis:
Designing Heterogeneous FPGAs with Multiple SBs. ARC 2007: 91-96 - 2006
- [c44]Alexandros Bartzas, Stylianos Mamagkakis, Georgios Pouiklis, David Atienza, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis:
Dynamic data type refinement methodology for systematic performance-energy design exploration of network applications. DATE 2006: 740-745 - [c43]Kostas Siozios, Konstantinos Tatas, Dimitrios Soudris, Antonios Thanailakis:
A novel methodology for designing high-performance and low-energy FPGA routing architecture. FPGA 2006: 224 - [c42]Kostas Siozios, Konstantinos Tatas, Dimitrios Soudris, Adonios Thanailakis:
Platform-based FPGA architecture: designing high-performance and low-power routing structure for realizing DSP applications. IPDPS 2006 - [c41]Kostas Siozios, Dimitrios Soudris, Adonios Thanailakis:
A novel methodology for designing high-performance and low-power FPGA interconnection targeting DSP applications. ISCAS 2006 - [c40]Kostas Siozios, Dimitrios Soudris, Antonios Thanailakis:
Designing Alternative FPGA Implementations Using Spatial Data from Hardware Resources. PATMOS 2006: 403-414 - [c39]Kostas Siozios, Dimitrios Soudris, Antonios Thanailakis:
Efficient Power Management Strategy of FPGAs Using a Novel Placement Technique. VLSI-SoC 2006: 204-209 - 2005
- [c38]Dimitrios Soudris, Spiridon Nikolaidis, Stilianos Siskos, Konstantinos Tatas, Kostas Siozios, George Koutroumpezis, Nikolaos Vassiliadis, Vasilios Kalenteridis, Haroula Pournara, Ilias Pappas, Adonios Thanailakis:
AMDREL: a novel low-energy FPGA architecture and supporting CAD tool design flow. ASP-DAC 2005: 3-4 - [c37]Minas Dasygenis, Erik Brockmeyer, Bart Durinck, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis:
A Memory Hierarchical Layer Assigning and Prefetching Technique to Overcome the Memory Performance/Energy Bottleneck. DATE 2005: 946-947 - [c36]Kostas Siozios, Konstantinos Tatas, George Koutroumpezis, D. J. Soudris, Adonios Thanailakis:
An Integrated Framework for Architecture Level Exploration of Reconfigurable Platform. FPL 2005: 658-661 - [c35]Kostas Siozios, Dimitrios Soudris, Adonios Thanailakis:
A Low-Energy FPGA: Architecture Design and Software-Supported Design Flow. FPL 2005: 707-708 - [c34]Kostas Siozios, George Koutroumpezis, Konstantinos Tatas, Dimitrios Soudris, Adonios Thanailakis:
DAGGER: A Novel Generic Methodology for FPGA Bitstream Generation and Its Software Tool Implementation. IPDPS 2005 - [c33]Nikolas Kroupis, Minas Dasygenis, Kleoniki Markou, Dimitrios Soudris, Adonios Thanailakis:
A modified spiral search motion estimation algorithm and its embedded system implementation. ISCAS (4) 2005: 3347-3350 - [c32]Minas Dasygenis, Erik Brockmeyer, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis:
Improving the Memory Bandwidth Utilization Using Loop Transformations. PATMOS 2005: 117-126 - [c31]Nikolas Kroupis, Minas Dasygenis, Dimitrios Soudris, Antonios Thanailakis:
A Modified Spiral Search Algorithm and its Embedded Hardware Implementation. IEC (Prague) 2005: 375-378 - [c30]Stylianos Mamagkakis, Christos Baloukas, David Atienza, Francky Catthoor, Dimitrios Soudris, José M. Mendías, Antonios Thanailakis:
Reducing Memory Fragmentation with Performance-Optimized Dynamic Memory Allocators in Network Applications. WWIC 2005: 354-364 - 2004
- [c29]Kostas Siozios, George Koutroumpezis, Konstantinos Tatas, Dimitrios Soudris, Adonios Thanailakis:
A Novel FPGA Configuration Bitstream Generation Algorithm and Tool Development. FPL 2004: 1116-1118 - [c28]Vasilios Kalenteridis, Haroula Pournara, Kostas Siozios, Konstantinos Tatas, George Koutroumpezis, Ilias Pappas, Spiridon Nikolaidis, Stilianos Siskos, D. J. Soudris, Adonios Thanailakis:
An Integrated FPGA Design Framework: Custom Designed FPGA Platform and Application Mapping Toolset Development. IPDPS 2004 - [c27]Evaggelia Theochari, Konstantinos Tatas, Dimitrios Soudris, Kostas Masselos, Konstantinos Potamianos, Spyros Blionas, Antonios Thanailakis:
A reusable IP FFT core for DSP applications. ISCAS (3) 2004: 621-624 - [c26]Minas Dasygenis, Erik Brockmeyer, Bart Durinck, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis:
Power, Performance and Area Exploration for Data Memory Assignment of Multimedia Applications. SAMOS 2004: 540-549 - [c25]Stylianos Mamagkakis, Alexandros Mpartzas, Georgios Pouiklis, David Atienza, Francky Catthoor, Dimitrios Soudris, Jose Manuel Mendias, Antonios Thanailakis:
Design of Energy Efficient Wireless Networks Using Dynamic Data Type Refinement Methodology. WWIC 2004: 26-37 - 2003
- [c24]Konstantinos Tatas, Kostas Siozios, Dimitrios Soudris, Adonios Thanailakis:
Power-Efficient Implementations of Multimedia Applications on Reconfigurable Platforms. FPL 2003: 1032-1035 - [c23]Dimitrios Soudris, Marios Kesoulis, Christos S. Koukourlis, Adonios Thanailakis, Spyros Blionas:
Alternative Direct Digital Frequency Synthesizer architectures with reduced memory size. ISCAS (2) 2003: 73-76 - [c22]Dimitrios Soudris, K. Sgouropoulos, Konstantinos Tatas, Vasilis F. Pavlidis, Adonios Thanailakis:
A methodology for implementing FIR filters and CAD tool development for designing RNS-based systems. ISCAS (5) 2003: 129-132 - [c21]Konstantinos Tatas, Kostas Siozios, Dimitrios Soudris, Adonios Thanailakis, Kostas Masselos, Konstantinos Potamianos, Spyros Blionas:
Power Optimization Methdology for Multimedia Applications Implementation on Reconfigurable Platforms. PATMOS 2003: 430-439 - [c20]Konstantinos Tatas, Kostas Siozios, Nikolaos Vassiliadis, D. J. Soudris, Spiridon Nikolaidis, Stilianos Siskos, Adonios Thanailakis:
FPGA Architecture Design and Toolset for Logic Implementation. PATMOS 2003: 607-616 - [c19]Marios Kesoulis, Dimitrios Soudris, Christos S. Koukourlis, Adonios Thanailakis:
Designing Low Power Direct Digital Frequency Synthesizers. VLSI-SOC 2003: 105-110 - 2002
- [c18]George Koutroumpezis, Konstantinos Tatas, Dimitrios Soudris, Spyros Blionas, Kostas Masselos, Adonios Thanailakis:
Architecture Design of a Reconfigurable Multiplier for Flexible Coarse-Grain Implementations. FPL 2002: 1027-1036 - [c17]Konstantinos Tatas, D. J. Soudris, D. Siomos, Minas Dasygenis, Adonios Thanailakis:
A novel division algorithm for parallel and sequential processing. ICECS 2002: 553-556 - [c16]Dimitrios Soudris, Minas Dasygenis, K. Mitroglou, Konstantinos Tatas, Adonios Thanailakis:
A full adder based methodology for scaling operation in residue number system. ICECS 2002: 891-894 - 2001
- [c15]Dimitrios Soudris, Vasilis F. Pavlidis, Adonios Thanailakis:
Designing low-power energy recovery adders based on pass transistor logic. ICECS 2001: 777-780 - [c14]Nikolas Kroupis, Minas Dasygenis, Antonios Argyriou, Konstantinos Tatas, Dimitrios Soudris, Antonios Thanailakis, Nikolaos D. Zervas, Constantinos E. Goutis:
Power, performance and area exploration of block matching algorithms mapped on programmable processors. ICIP (3) 2001: 728-731 - [c13]Ioannis M. Thoidis, Dimitrios Soudris, Jean-Marc Fernandez, Adonios Thanailakis:
The circuit design of multiple-valued logic voltage-mode adders. ISCAS (4) 2001: 162-165 - [c12]D. J. Soudris, Minas Dasygenis, Spyridoula K. Vasilopoulou, Adonios Thanailakis:
A CAD tool for architecture level exploration and automatic generation of RNS converters. ISCAS (4) 2001: 730-733 - 2000
- [c11]D. J. Soudris, Minas Dasygenis, Adonios Thanailakis:
Designing RNS and QRNS full adder based converters. ISCAS 2000: 20-23 - [c10]Nikolaos D. Zervas, Dimitrios Soudris, Spyros Theoharis, Constantinos E. Goutis, Adonios Thanailakis:
A methodology for the behavioral-level event-driven power management of digital receivers. ISCAS 2000: 589-592 - [c9]Dimitrios Soudris, Minas Perakis, Haris Mizas, Vasilios A. Mardiris, Kosfas Katis, Chrissavgi Dre, A. E. Tzimas, E. G. Metaxakis, Grigorios Kalivas, Nikolaos D. Zervas, Spyros Theoharis, George Theodoridis, Adonios Thanailakis, Constantinos E. Goutis:
Low power design of a multi-mode transceiver. ISCAS 2000: 721-724 - [c8]Dimitrios Soudris, Nikolaos D. Zervas, Antonios Argyriou, Minas Dasygenis, Konstantinos Tatas, Constantinos E. Goutis, Adonios Thanailakis:
Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Applications. PATMOS 2000: 243-254 - 1999
- [c7]C. Z. Lolas, Dimitrios Soudris, Ioannis Karafyllidis, Adonios Thanailakis:
A new adiabatic technique for designing low power array architectures. ICECS 1999: 795-798 - [c6]I. Thoidis, D. J. Soudris, Ioannis Karafyllidis, Adonios Thanailakis:
The design of low power multiple-valued logic encoder and decoder circuits. ICECS 1999: 1623-1626 - [c5]Ioannis Karafyllidis, Stelios Mavridis, Dimitrios Soudris, Adonios Thanailakis:
Estimation of power dissipation in glitching using complex-time cellular automata. ICECS 1999: 1639-1642 - [c4]George Ch. Sirakoulis, Ioannis Karafyllidis, Adonios Thanailakis:
Genetic partitioning and placement for VLSI circuits. ICECS 1999: 1647-1650 - [c3]M. Perakis, A. E. Tzimas, E. G. Metaxakis, Dimitrios Soudris, Grigorios A. Kalivas, C. Katis, Chrissavgi Dre, Constantinos E. Goutis, Adonios Thanailakis, Thanos Stouraitis:
The VLSI implementation of a baseband receiver for DECT-based portable applications. ISCAS (1) 1999: 198-201 - 1998
- [c2]I. Thoidis, Dimitrios Soudris, Ioannis Karafyllidis, Adonios Thanailakis, Thanos Stouraitis:
Multiple-Valued Logic Voltage-Mode Storage Circuits Based On True-Single-Phase Clocked Logic. Great Lakes Symposium on VLSI 1998: 83-88 - 1996
- [c1]Dimitrios Soudris, George Theodoridis, S. Theoharis, Adonios Thanailakis:
Low-power design of array architectures. ICECS 1996: 120-123
Informal and Other Publications
- 2007
- [i1]Minas Dasygenis, Erik Brockmeyer, Bart Durinck, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis:
A Memory Hierarchical Layer Assigning and Prefetching Technique to Overcome the Memory Performance/Energy Bottleneck. CoRR abs/0710.4656 (2007)
Coauthor Index
Dimitrios Soudris
aka: D. J. Soudris
aka: D. J. Soudris
[j41] [j40] [j39] [j37] [j36] [j35] [j34] [j33] [j32] [j29] [j28] [j27] [j22] [j20] [c45] [c44] [c43] [c42] [c41] [c40] [c39] [c38] [c37] [c36] [c35] [c34] [c33] [c32] [c31] [c30] [c29] [c28] [c27] [c26] [c25] [c24] [c23] [c22] [c21] [c20] [c19] [c18] [c17] [c16] [c15] [c14] [c13] [c12] [c11] [c10] [c9] [c8] [c7] [c6] [c5] [c3] [c2] [c1] [i1]
Philippos Tsalides
aka: Philippos G. Tsalides
aka: Philippos G. Tsalides
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