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ORCIDKonstantinos Tatas
Person information
- affiliation: Frederick University, Department of Computer Science and Engineering, Nicosia, Cyprus
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2020 – today
- 2024
[c32]N. Ioannou, Konstantinos Tatas, A. Constantinides, Costas Kyriacou:
WIDE: Worksheet Integrated Development Environment for Arduino-Based Embedded System Design. MOCAST 2024: 1-5- [c31]Konstantinos Tatas, Christos Markides, Victoras Kassianides, Nicos Hadjisofokli:
Artemis: IoT-Based Shooting Range Management System. MOCAST 2024: 1-4 - 2023
- [c30]V. Samaras, Konstantinos Tatas, Antonios Lontos:
A Low-Cost Real-Time Cyber Physical System for Overcoming Excess Braking Issues In Race Cars. MOCAST 2023: 1-4 - 2021
- [c29]Konstantinos Tatas
:
Towards an Analytical Model of Latency in Deflection Routing: A Stochastic Process Approach for Bufferless NoCs. MOCAST 2021: 1-5 - [c28]Konstantinos Tatas, Ahmad Al-Zoubi, A. Antoniou, D. Zolotareva:
iPONICS: IoT Monitoring and Control for Hydroponics. MOCAST 2021: 1-5 - 2020
- [j11]Ahmad Al-Zoubi, Konstantinos Tatas, Costas Kyriacou:
Fuzzy classification of OpenCL programs targeting heterogeneous systems. J. Intell. Fuzzy Syst. 39(5): 7189-7202 (2020)
2010 – 2019
- 2018
- [c27]Ahmad Al-Zoubi, Konstantinos Tatas, Costas Kyriacou:
Towards Dynamic Multi-task Schedulling of OpenCL Programs on Emerging CPU-GPU-FPGA Heterogeneous Platforms: A Fuzzy Logic Approach. CloudCom 2018: 247-250 - [c26]Ahmad Al-Zoubi, Konstantinos Tatas, Costas Kyriacou:
Design space exploration of the KNN imputation on FPGA. MOCAST 2018: 1-4 - [c25]Konstantinos Tatas:
High-performance 3D NoC bufferless router with approximate priority comparison. MOCAST 2018: 1-4 - 2017
- [j10]Konstantinos Tatas, Chrysostomos Chrysostomou:
Hardware implementation of dynamic fuzzy logic based routing in Network-on-Chip. Microprocess. Microsystems 52: 80-88 (2017) - [c24]Konstantinos Tatas, Savvas Sava, Costas Kyriacou:
3DBUFFBLESS: A novel buffered-bufferless hybrid router for 3D Networks-on-Chip. PATMOS 2017: 1-8 - 2016
- [c23]Konstantinos Tatas, Chrysostomos Chrysostomou:
Adaptive Networks-on-Chip Routing with Fuzzy Logic Control. DSD 2016: 138-145 - 2014
- [c22]Konstantinos Tatas, S. Sawa, Costas Kyriacou:
Low-cost fault-tolerant routing for regular topology NoCs. ICECS 2014: 566-569 - 2013
- [j9]Konstantinos Tatas, Kostas Siozios, Alexandros Bartzas, Costas Kyriacou, Dimitrios Soudris:
A Novel Prototyping and Evaluation Framework for NoC-Based MPSoC. Int. J. Adapt. Resilient Auton. Syst. 4(3): 1-24 (2013) - 2012
- [c21]Konstantinos Tatas, Chrysostomos Chrysostomou:
A novel fuzzy logic based bufferless routing algorithm for low-power NoCs. BCFIC 2012: 106-112 - [c20]Chrysostomos Chrysostomou, Konstantinos Tatas, A. R. Runcan:
A Dynamic Fuzzy Logic Based Routing Scheme for Bufferless NoCs. CSE 2012: 295-302
2000 – 2009
- 2008
- [j8]Konstantinos Tatas, Costas Kyriacou, Paraskevas Evripidou, Pedro Trancoso, Stephan Wong:
Rapid Prototyping of the Data-Driven Chip-Multiprocessor (d2-CMP) Using FPGAs. Parallel Process. Lett. 18(2): 291-306 (2008) - 2007
- [j7]Konstantinos Tatas, George Koutroumpezis, Dimitrios Soudris, Adonios Thanailakis:
Architecture design of a coarse-grain reconfigurable multiply-accumulate unit for data-intensive applications. Integr. 40(2): 74-93 (2007) - 2006
- [j6]Nikolas Kroupis, Nikolaos D. Zervas, Minas Dasygenis, Konstantinos Tatas, Antonios Argyriou, Dimitrios Soudris, Antonios Thanailakis:
Behavioral-Level Performance and Power Exploration of Data-Intensive Applications Mapped on Programmable Processors. J. VLSI Signal Process. 44(1-2): 153-171 (2006) - [c19]Kostas Siozios, Konstantinos Tatas, Dimitrios Soudris, Antonios Thanailakis:
A novel methodology for designing high-performance and low-energy FPGA routing architecture. FPGA 2006: 224 - [c18]Kostas Siozios, Konstantinos Tatas, Dimitrios Soudris, Adonios Thanailakis:
Platform-based FPGA architecture: designing high-performance and low-power routing structure for realizing DSP applications. IPDPS 2006 - 2005
- [j5]Kostas Siozios, George Koutroumpezis, Konstantinos Tatas, Nikolaos Vassiliadis, Vasilios Kalenteridis, Haroula Pournara, Ilias Pappas, Dimitrios Soudris, Antonios Thanailakis, Spiridon Nikolaidis, Stilianos Siskos:
A Novel FPGA Architecture and an Integrated Framework of CAD Tools for Implementing Applications. IEICE Trans. Inf. Syst. 88-D(7): 1369-1380 (2005) - [j4]Konstantinos Tatas, Dimitrios Soudris, D. Siomos, Adonios Thanailakis:
A Novel Division Algorithm and Architectures for Parallel and Sequential Processing. J. Circuits Syst. Comput. 14(2): 281-296 (2005) - [j3]Konstantinos Tatas, Dimitrios Soudris, Adonios Thanailakis:
Memory power optimization of hardware implementations of multimedia applications onto FPGA platforms. J. Embed. Comput. 1(3): 353-362 (2005) - [j2]Vasilios Kalenteridis, Haroula Pournara, Kostas Siozios, Konstantinos Tatas, Nikolaos Vassiliadis, Ilias Pappas, George Koutroumpezis, Spiridon Nikolaidis, Stilianos Siskos, D. J. Soudris:
A complete platform and toolset for system implementation on fine-grain reconfigurable hardware. Microprocess. Microsystems 29(6): 247-259 (2005) - [c17]Dimitrios Soudris, Spiridon Nikolaidis, Stilianos Siskos, Konstantinos Tatas, Kostas Siozios, George Koutroumpezis, Nikolaos Vassiliadis, Vasilios Kalenteridis, Haroula Pournara, Ilias Pappas, Adonios Thanailakis:
AMDREL: a novel low-energy FPGA architecture and supporting CAD tool design flow. ASP-DAC 2005: 3-4 - [c16]Kostas Siozios, Konstantinos Tatas, George Koutroumpezis, D. J. Soudris, Adonios Thanailakis:
An Integrated Framework for Architecture Level Exploration of Reconfigurable Platform. FPL 2005: 658-661 - [c15]Kostas Siozios, George Koutroumpezis, Konstantinos Tatas, Dimitrios Soudris, Adonios Thanailakis:
DAGGER: A Novel Generic Methodology for FPGA Bitstream Generation and Its Software Tool Implementation. IPDPS 2005 - 2004
- [c14]Kostas Siozios, George Koutroumpezis, Konstantinos Tatas, Dimitrios Soudris, Adonios Thanailakis:
A Novel FPGA Configuration Bitstream Generation Algorithm and Tool Development. FPL 2004: 1116-1118 - [c13]Vasilios Kalenteridis, Haroula Pournara, Kostas Siozios, Konstantinos Tatas, George Koutroumpezis, Ilias Pappas, Spiridon Nikolaidis, Stilianos Siskos, D. J. Soudris, Adonios Thanailakis:
An Integrated FPGA Design Framework: Custom Designed FPGA Platform and Application Mapping Toolset Development. IPDPS 2004 - [c12]Evaggelia Theochari, Konstantinos Tatas, Dimitrios Soudris, Kostas Masselos, Konstantinos Potamianos, Spyros Blionas, Antonios Thanailakis:
A reusable IP FFT core for DSP applications. ISCAS (3) 2004: 621-624 - 2003
- [j1]Konstantinos Tatas, Minas Dasygenis, Nikolas Kroupis, Antonios Argyriou, Dimitrios Soudris, Antonios Thanailakis:
Data memory power optimization and performance exploration of embedded systems for implementing motion estimation algorithms. Real Time Imaging 9(6): 371-386 (2003) - [c11]Konstantinos Tatas, Kostas Siozios, Dimitrios Soudris, Adonios Thanailakis:
Power-Efficient Implementations of Multimedia Applications on Reconfigurable Platforms. FPL 2003: 1032-1035 - [c10]Dimitrios Soudris, K. Sgouropoulos, Konstantinos Tatas, Vasilis F. Pavlidis, Adonios Thanailakis:
A methodology for implementing FIR filters and CAD tool development for designing RNS-based systems. ISCAS (5) 2003: 129-132 - [c9]Konstantinos Tatas, Kostas Siozios, Dimitrios Soudris, Adonios Thanailakis, Kostas Masselos, Konstantinos Potamianos, Spyros Blionas:
Power Optimization Methdology for Multimedia Applications Implementation on Reconfigurable Platforms. PATMOS 2003: 430-439 - [c8]Konstantinos Tatas, Kostas Siozios, Nikolaos Vassiliadis, D. J. Soudris, Spiridon Nikolaidis, Stilianos Siskos, Adonios Thanailakis:
FPGA Architecture Design and Toolset for Logic Implementation. PATMOS 2003: 607-616 - 2002
- [c7]George Koutroumpezis, Konstantinos Tatas, Dimitrios Soudris, Spyros Blionas, Kostas Masselos, Adonios Thanailakis:
Architecture Design of a Reconfigurable Multiplier for Flexible Coarse-Grain Implementations. FPL 2002: 1027-1036 - [c6]Konstantinos Tatas, D. J. Soudris, D. Siomos, Minas Dasygenis, Adonios Thanailakis:
A novel division algorithm for parallel and sequential processing. ICECS 2002: 553-556 - [c5]Dimitrios Soudris, Minas Dasygenis, K. Mitroglou, Konstantinos Tatas, Adonios Thanailakis:
A full adder based methodology for scaling operation in residue number system. ICECS 2002: 891-894 - 2001
- [c4]Minas Dasygenis, Nikolas Kroupis, Antonios Argyriou, Konstantinos Tatas, Dimitrios Soudris, Nikolaos D. Zervas:
Data and instruction memory exploration of embedded systems for multimedia applications. ICASSP 2001: 1149-1152 - [c3]Nikolas Kroupis, Minas Dasygenis, Antonios Argyriou, Konstantinos Tatas, Dimitrios Soudris, Antonios Thanailakis, Nikolaos D. Zervas, Constantinos E. Goutis:
Power, performance and area exploration of block matching algorithms mapped on programmable processors. ICIP (3) 2001: 728-731 - [c2]Konstantinos Tatas, Antonios Argyriou, Minas Dasygenis, Dimitrios Soudris, Nikolaos D. Zervas:
Memory Hierarchy Optimization of Multimedia Applications on Programmable Embedded Cores 1. ISQED 2001: 456-461 - 2000
- [c1]Dimitrios Soudris, Nikolaos D. Zervas, Antonios Argyriou, Minas Dasygenis, Konstantinos Tatas, Constantinos E. Goutis, Adonios Thanailakis:
Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Applications. PATMOS 2000: 243-254
Coauthor Index
aka: D. J. Soudris
aka: Antonios Thanailakis
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