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2020 – today
- 2023
[j5]Senling Wang
, Xihong Zhou, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima:
Test Point Insertion for Multi-Cycle Power-On Self-Test. ACM Trans. Design Autom. Electr. Syst. 28(3): 46:1-46:21 (2023)- [c12]Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima, Oussama Laouamri, Naveen Khanna, Jeff Mayer, Nilanjan Mukherjee:
A New Framework for RTL Test Points Insertion Facilitating a "Shift-Left DFT" Strategy. ITC 2023: 1-10 - 2021
- [c11]Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima:
A Power Reduction Method for Scan Testing in Ultra-Low Power Designs. ATS 2021: 141 - 2020
- [j4]Hanan T. Al-Awadhi, Tomoki Aono, Senling Wang, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima:
FF-Control Point Insertion (FF-CPI) to Overcome the Degradation of Fault Detection under Multi-Cycle Test for POST. IEICE Trans. Inf. Syst. 103-D(11): 2289-2301 (2020)
2010 – 2019
- 2018
- [j3]Senling Wang, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Jun Matsushima:
Automotive Functional Safety Assurance by POST with Sequential Observation. IEEE Des. Test 35(3): 39-45 (2018) - [c10]Senling Wang, Tomoki Aono, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima:
Capture-Pattern-Control to Address the Fault Detection Degradation Problem of Multi-cycle Test in Logic BIST. ATS 2018: 155-160 - [c9]Senling Wang, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima:
Fault-detection-strengthened method to enable the POST for very-large automotive MCU in compliance with ISO26262. ETS 2018: 1-2 - [c8]Koji Asami, Yoshiro Tamura, Haruo Kobayashi, Jun Matsushima, Yoichi Maeda, Kazumi Hatayama:
Innovative practices on test in Japan. VTS 2018: 1 - 2017
- [j2]Shinichi Shibahara, Chikafumi Takahashi, Kazuki Fukuoka, Yuko Kitaji, Takahiro Irita, Hirotaka Hara, Yasuhisa Shimazaki, Jun Matsushima:
A 16 nm FinFET Heterogeneous Nona-Core SoC Supporting ISO26262 ASIL B Standard. IEEE J. Solid State Circuits 52(1): 77-88 (2017) - [c7]Yoichi Maeda, Jun Matsushima, Ron Press:
Automotive IC On-line Test Techniques and the Application of Deterministic ATPG-Based Runtime Test. ATS 2017: 237-241 - 2016
- [c6]Hiroyuki Iwata, Jun Matsushima:
Multi-configuration Scan Structure for Various Purposes. ATS 2016: 131 - [c5]Senling Wang, Hanan T. Al-Awadhi, Soh Hamada, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Jun Matsushima:
Structure-Based Methods for Selecting Fault-Detection-Strengthened FF under Multi-cycle Test with Sequential Observation. ATS 2016: 209-214 - [c4]Chikafumi Takahashi, Shinichi Shibahara, Kazuki Fukuoka, Jun Matsushima, Yuko Kitaji, Yasuhisa Shimazaki, Hirotaka Hara, Takahiro Irita:
4.5 A 16nm FinFET heterogeneous nona-core SoC complying with ISO26262 ASIL-B: Achieving 10-7 random hardware failures per hour reliability. ISSCC 2016: 80-81 - 2012
- [j1]Masanori Kurimoto, Jun Matsushima, Shigeki Ohbayashi, Yoshiaki Fukui, Michio Komoda, Nobuhiro Tsuda:
A Yield and Reliability Improvement Methodology Based on Logic Redundant Repair with a Repairable Scan Flip-Flop Designed by Push Rule. ACM Trans. Design Autom. Electr. Syst. 17(2): 17:1-17:22 (2012) - [c3]Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima, Masahiro Takakura:
An Effective At-Speed Scan Testing Approach Using Multiple-Timing Clock Waveforms. Asian Test Symposium 2012: 1 - 2010
- [c2]Masanori Kurimoto, Jun Matsushima, Shigeki Ohbayashi, Yoshiaki Fukui:
A yield improvement methodology based on logic redundant repair with a repairable scan flip-flop designed by push rule. ISQED 2010: 184-190
2000 – 2009
- 2008
- [c1]Jun Matsushima, Yoichi Maeda, Masahiro Takakura:
CooLBIST: An Effective Approach of Test Power Reduction for LBIST. ATS 2008: 264
Coauthor Index
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