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ORCIDCharles H. Stapper
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2000 – 2009
- 2000
[j16]Charles H. Stapper:
LSI yield modeling and process monitoring. IBM J. Res. Dev. 44(1): 112-118 (2000)
1990 – 1999
- 1995
- [j15]Wayne F. Ellis, John E. Barth Jr., Sri Divakaruni, Jeffrey H. Dreibelbis, Anatol Furman, Erik L. Hedberg, Hsing-San Lee, Thomas M. Maffitt, Christopher P. Miller, Charles H. Stapper, Howard L. Kalter:
Multipurpose DRAM architecture for optimal power, performance, and product flexibility. IBM J. Res. Dev. 39(1-2): 51-62 (1995) - 1994
- [j14]Israel Koren, Zahava Koren, Charles H. Stapper:
A statistical study of defect maps of large area VLSI IC's. IEEE Trans. Very Large Scale Integr. Syst. 2(2): 249-256 (1994) - [c4]Charles H. Stapper, A. J. Rideout:
On Fractal Yield Models: A Statistical Paradox. DFT 1994: 83-87 - 1993
- [j13]Israel Koren, Zahava Koren, Charles H. Stapper:
A Unified Negative-Binomial Distribution for Yield Analysis of Defect-Tolerant Circuits. IEEE Trans. Computers 42(6): 724-734 (1993) - [j12]Charles H. Stapper:
Improved Yield Models for Fault-Tolerant Memory Chips. IEEE Trans. Computers 42(7): 872-881 (1993) - [c3]Charles H. Stapper, J. A. Patrick, R. J. Rosner:
Yield Model for ASIC and Processor Chips. DFT 1993: 136-143 - 1992
- [j11]Charles H. Stapper, Hsing-San Lee:
Synergistic Fault-Tolerance for Memory Chips. IEEE Trans. Computers 41(9): 1078-1087 (1992) - [c2]Charles H. Stapper:
A New Statistical Approach for Fault-Tolerant VLSI Systems. FTCS 1992: 356-365 - 1991
- [j10]John A. Fifield, Charles H. Stapper:
High-speed on-chip ECC for synergistic fault-tolerance memory chips. IEEE J. Solid State Circuits 26(10): 1449-1452 (1991) - [j9]Charles H. Stapper:
Statistics associated with spatial fault simulation used for evaluating integrated circuit yield enhancement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(3): 399-406 (1991) - 1990
- [j8]Howard L. Kalter, Charles H. Stapper, John E. Barth Jr., John DiLorenzo, Charles E. Drake, John A. Fifield, Gordon A. Kelley, Scott C. Lewis, Willem B. van der Hoeven, James A. Yankosky:
A 50-ns 16-Mb DRAM with a 10-ns data rate and on-chip ECC. IEEE J. Solid State Circuits 25(5): 1118-1128 (1990)
1980 – 1989
- 1989
- [j7]Charles H. Stapper:
Large-Area Fault Clusters and Fault Tolerance in VLSI Circuits: A Review. IBM J. Res. Dev. 33(2): 162-173 (1989) - [j6]Charles H. Stapper:
Simulation of spatial fault distributions for integrated circuit yield estimations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(12): 1314-1318 (1989) - 1986
- [c1]Andrzej J. Strojwas, Clark Beck, Dennis Buss, Tülin Erdim Mangir, Charles H. Stapper:
Yield of VLSI circuits: myths vs. reality (panel). DAC 1986: 234-235 - 1984
- [j5]Charles H. Stapper:
Modeling of Defects in Integrated Circuit Photolithographic Patterns. IBM J. Res. Dev. 28(4): 461-475 (1984) - [j4]Charles H. Stapper:
Yield Model for Fault Clusters Within Integrated Circuits. IBM J. Res. Dev. 28(5): 636-640 (1984) - 1983
- [j3]Charles H. Stapper:
Modeling of Integrated Circuit Defect Sensitivities. IBM J. Res. Dev. 27(6): 549-557 (1983) - 1980
- [j2]Charles H. Stapper, A. N. McLaren, M. Dreckmann:
Yield Model for Productivity Optimization of VLSI Memory Chips with Redundancy and Partially Good Product. IBM J. Res. Dev. 24(3): 398-409 (1980)
1970 – 1979
- 1976
- [j1]Charles H. Stapper:
LSI Yield Modeling and Process Monitoring. IBM J. Res. Dev. 20(3): 228-234 (1976)
Coauthor Index
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