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Weixin Gai
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2020 – today
- 2024
- [j8]Bingyi Ye, Guangdong Wu, Weixin Gai, Kai Sheng, Yandong He:
A Five-Tap Delay-Line-Based Feed-Forward-Equalizer for 200-Gb/s Wireline Receiver in 28-nm CMOS. IEEE J. Solid State Circuits 59(1): 19-28 (2024) - [c30]Boyang Zhang, Zhifei Wang, Zeze Feng, Tianchen Ye, Bingyi Ye, Zixu Wang, Weixin Gai:
A 200-Gb/s PAM-4 Transmitter with 1.6-Vppd Output Swing and Clock Skew Correction in 12-nm FinFET. VLSI Technology and Circuits 2024: 1-2 - 2023
- [j7]Bingyi Ye, Kai Sheng, Weixin Gai, Haowei Niu, Boyang Zhang, Yandong He, Song Jia, Congcong Chen, Jiaqi Yu:
A 2.29-pJ/b 112-Gb/s Wireline Transceiver With RX Four-Tap FFE for Medium-Reach Applications in 28-nm CMOS. IEEE J. Solid State Circuits 58(1): 19-29 (2023) - [j6]Kai Sheng, Haowei Niu, Boyang Zhang, Weixin Gai, Bingyi Ye, Hang Zhou, Congcong Chen:
A 4.6-pJ/b 200-Gb/s Analog DP-QPSK Coherent Optical Receiver in 28-nm CMOS. IEEE J. Solid State Circuits 58(1): 45-56 (2023) - [c29]Bingyi Ye, Guangdong Wu, Weixin Gai, Kai Sheng, Yandong He:
A 0.43pJ/b 200Gb/s 5-Tap Delay-Line-Based Receiver FFE with Low-Frequency Equalization in 28nm CMOS. ISSCC 2023: 112-113 - [c28]Kai Sheng, Weixin Gai, Zeze Feng, Haowei Niu, Bingyi Ye, Hang Zhou:
A 128Gb/s PAM-4 Transmitter with Programmable-Width Pulse Generator and Pattern-Dependent Pre-Emphasis in 28nm CMOS. ISSCC 2023: 120-121 - 2022
- [j5]Cece Huang, Weixin Gai, Yuanfu Zhao, Yafei Ji, Fei Chu, Tieliang Zhang:
A Residue Amplifier with 85 dB DC Gain and 15 GHz Closed-Loop Bandwidth for 14-Bit 3GSPS Pipeline ADC. Circuits Syst. Signal Process. 41(12): 6694-6708 (2022) - [c27]Cece Huang, Yuanfu Zhao, Yafei Ji, Xin Yang, Tieliang Zhang, Weixin Gai:
An Input Buffer with 85dB SFDR for High-Speed Pipeline ADC. ICTA 2022: 52-53 - [c26]Ninghuang Li, Weixin Gai, Bingyi Ye, Haowei Niu, Lei Lu:
A High-Linearity 14GHz 7b Phase Interpolator for Ultra-High-Speed Wireline Applications. ISCAS 2022: 2487-2490 - [c25]Bingyi Ye, Kai Sheng, Weixin Gai, Haowei Niu, Boyang Zhang, Yandong He, Song Jia, Congcong Chen, Jiaqi Yu:
A 2.29pJ/b 112Gb/s Wireline Transceiver with RX 4-Tap FFE for Medium-Reach Applications in 28nm CMOS. ISSCC 2022: 118-120 - [c24]Kai Sheng, Haowei Niu, Boyang Zhang, Weixin Gai, Bingyi Ye, Hang Zhou, Congcong Chen:
A 4.6pJ/b 200Gb/s Analog DP-QPSK Coherent Optical Receiver in 28nm CMOS. ISSCC 2022: 282-284 - 2021
- [j4]Xiao Xiang, Weixin Gai, Ai He, Hang Zhou, Dong Yanchi:
Equal-slope baud-rate CDR algorithm with optimized eye opening. Microelectron. J. 114: 105138 (2021) - [j3]Ai He, Weixin Gai, Bingyi Ye, Boyang Zhang, Kai Sheng, Yuanliang Li:
56 Gb/s PAM4 receiver with an overshoot compensation scheme in 28 nm CMOS technology. Microelectron. J. 116: 105236 (2021) - [c23]Ai He, Weixin Gai, Kai Sheng, Ninghuang Li:
An Adaptive DFE Using Pattern-Dependent Data-Level Reference in 28 nm CMOS Technology. ASICON 2021: 1-4 - [c22]Kai Sheng, Linqi Shi, Weixin Gai, Qianting Hua, Peng Lin:
A 2-Bit 4-Level 4-Wire 56Gb/s Transceiver in 14nm FinFET. ISCAS 2021: 1-5 - [c21]Liangxiao Tang, Weixin Gai, Chih-Kong Ken Yang, Bingyi Ye, Congcong Chen:
A 25Gb/s 185mW PAM-4 Receiver with 4-Tap Adaptive DFE and Sampling Clock Optimization in 55nm CMOS. ISCAS 2021: 1-4 - [c20]Dong Yanchi, Weixin Gai, Xiao Xiang, Haowei Niu:
A 14GHz Cascade Differential-Capacitor-Based DCO with Resistor-Biased Buffer. ISCAS 2021: 1-5 - [c19]Boyang Zhang, Weixin Gai, Haowei Niu, Bingyi Ye, Kai Sheng, Tianjian Zuo, Lei Liu:
Analog Signal Processing Circuits for a 400Gb/s 16QAM Optical Coherent Receiver. ISCAS 2021: 1-5
2010 – 2019
- 2019
- [c18]Sheng Zhang, Song Jia, Hanzun Zhang, Rongshan Wei, Weixin Gai:
Design of an Adaptive Loop Gain Controller Based on Auto-correlation Detection Scheme in All-Digital Phase-Locked Loop. ASICON 2019: 1-4 - [c17]Ai He, Weixin Gai, Yufan Feng, Zhongzhu Pu, Xiao Xiang:
Double-Comparison Settling Error Correction Scheme for Binary Scaled SAR ADCs. ISCAS 2019: 1-4 - [c16]Xiao Xiang, Weixin Gai, Linqi Shi, Ai He, Kai Sheng:
An 8-12GHz 0.92° Phase Error Quadrature Clock Generator Based on Two-Stage Poly Phase Filter with Intermediate Point Compensation. ISCAS 2019: 1-5 - 2018
- [c15]Yinxuan Lyu, Jianhua Feng, Chenfeng Tu, Linqi Shi, Hongfei Ye, Weixin Gai, Dunshan Yu:
A 108fsrms 0.45mW 100MS/s 1.25MHz bandwidth multi-bit ΔΣ time-to-digital converter with dynamic element matching. ISCAS 2018: 1-5 - [c14]Linqi Shi, Weixin Gai, Jichao Huang, Liangxiao Tang, Xiao Xiang:
A Sub-ps Integrated-Jitter 10 GHz ADPLL with Fractional Capacitor. ISCAS 2018: 1-4 - [c13]Linqi Shi, Weixin Gai, Xiaoting Zhi, Liangxiao Tang, Xiao Xiang:
An 8.52-11.34 GHz 0.34° Phase Error Quadrature Clock Generator with Time-Voltage-Time Convertor. ISCAS 2018: 1-4 - [c12]Liangxiao Tang, Weixin Gai, Linqi Shi, Xiao Xiang, Kai Sheng, Ai He:
A 32Gb/s 133mW PAM-4 transceiver with DFE based on adaptive clock phase and threshold voltage in 65nm CMOS. ISSCC 2018: 114-116 - 2017
- [c11]Liangxiao Tang, Weixin Gai, Linqi Shi, Xiao Xiang:
A 40 Gb/s 74.9 mW PAM4 receiver with novel clock and data recovery. ISCAS 2017: 1-4 - 2016
- [c10]Liangxiao Tang, Weixin Gai, Linqi Shi:
PAM4 receiver with adaptive threshold voltage and adaptive decision feedback equalizer. ISCAS 2016: 2246-2249 - [c9]Shihao Li, Weixin Gai, Xiao Xiang, Liangxiao Tang, Jichao Huang, Tong Zhao, Xiaoting Zhi:
A 1.27mW 20Gbps 1: 16 DEMUX with a symmetrical-edge-delay sense amplifier. ISCAS 2016: 2419-2422 - 2015
- [c8]Yang Wang, Weixin Gai:
A 2-tap 40-Gb/s 4-PAM transmitter with level selection based pre-emphasis. ISCAS 2015: 333-336 - [c7]Jincai Liu, Weixin Gai, Liangxiao Tang:
A novel 6-Gbps half-rate SST transmitter with impedance calibration and adjustable pre-emphasis. ISCAS 2015: 341-344 - 2013
- [c6]Yaming Zhang, Weixin Gai:
SSC tracking analysis and a deeper-SSC estimator. ISCAS 2013: 1408-1411 - [c5]Bohan Wu, Weixin Gai, Te Han:
A novel frequency search algorithm to achieve fast locking without phase tracking in ADPLL. ISCAS 2013: 2464-2467 - [c4]Te Han, Weixin Gai:
A 2.7-GHz digitally-controlled ring oscillator with supply sensitivity of 0.0014%-fDCO/1%-VDD using digital current-regulated tuning. ISCAS 2013: 2690-2693
2000 – 2009
- 2009
- [j2]Yasuo Hidaka, Weixin Gai, Takeshi Horie, Jian Hong Jiang, Yoichi Koyanagi, Hideki Osone:
A 4-Channel 1.25-10.3 Gb/s Backplane Transceiver Macro With 35 dB Equalizer and Sign-Based Zero-Forcing Adaptive Control. IEEE J. Solid State Circuits 44(12): 3547-3559 (2009) - [c3]Yasuo Hidaka, Weixin Gai, Takeshi Horie, Jian Hong Jiang, Yoichi Koyanagi, Hideki Osone:
A 4-channel 10.3Gb/s backplane transceiver macro with 35dB equalizer and sign-based zero-forcing adaptive control. ISSCC 2009: 188-189 - 2007
- [c2]Jian Hong Jiang, Weixin Gai, Akira Hattori, Yasuo Hidaka, Takeshi Horie, Yoichi Koyanagi, Hideki Osone:
Design Consideration of 6.25 Gbps Signaling for High-Performance Server. ASP-DAC 2007: 854-857 - [c1]Yasuo Hidaka, Weixin Gai, Akira Hattori, Takeshi Horie, Jian Jiang, Kouichi Kanda, Yoichi Koyanagi, Satoshi Matsubara, Hideki Osone:
A 4-Channel 3.1/10.3Gb/s Transceiver Macro with a Pattern-Tolerant Adaptive Equalizer. ISSCC 2007: 442-443 - 2003
- [j1]Xingjun Wu, Hongyi Chen, Yihe Sun, Weixin Gai:
A Fully-Pipeline Linear Systolic Architecture for Modular Multiplier in Public-Key Crypto-Systems. J. VLSI Signal Process. 33(1-2): 191-197 (2003)
Coauthor Index
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last updated on 2024-10-18 20:26 CEST by the dblp team
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