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Nigel P. Topham
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- affiliation: University of Edinburgh, UK
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2020 – today
- 2024
- [i2]Alexander Strachan, Nigel P. Topham:
Integrating HW/SW Functionality for Flexible Wireless Radio. CoRR abs/2412.10590 (2024) - 2023
- [c52]Heba Salem, Nigel P. Topham:
Run-time integrity monitoring of untrustworthy analog front-ends. DATE 2023: 1-6 - 2021
- [c51]Heba Salem, Nigel P. Topham:
Trustworthy computing on untrustworthy and Trojan-infected on-chip interconnects. ETS 2021: 1-2 - [c50]Heba Salem, Nigel P. Topham:
Detecting denial-of-service hardware Trojans in DRAM-based memory systems. ICECS 2021: 1-6 - 2020
- [j12]Martin Kristien
, Tom Spink
, Brian Campbell
, Susmit Sarkar
, Ian Stark, Björn Franke, Igor Böhm, Nigel P. Topham:
Fast and Correct Load-Link/Store-Conditional Instruction Handling in DBT Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(11): 3544-3554 (2020)
2010 – 2019
- 2019
- [c49]Saumay Dublish, Vijay Nagarajan, Nigel P. Topham:
Poise: Balancing Thread-Level Parallelism and Memory System Performance in GPUs Using Machine Learning. HPCA 2019: 492-505 - [c48]Martin Kristien, Tom Spink
, Harry Wagstaff, Björn Franke
, Igor Böhm, Nigel P. Topham:
Mitigating JIT compilation latency in virtual execution environments. VEE 2019: 101-107 - 2018
- [j11]Christopher Thompson
, Miles Gould
, Nigel P. Topham
:
High Speed Cycle-Approximate Simulation of Embedded Cache-Incoherent and Coherent Chip-Multiprocessors. Int. J. Parallel Program. 46(6): 1247-1282 (2018) - 2017
- [c47]Saumay Dublish, Vijay Nagarajan, Nigel P. Topham:
Evaluating and mitigating bandwidth bottlenecks across the memory hierarchy in GPUs. ISPASS 2017: 239-248 - 2016
- [j10]Saumay Dublish, Vijay Nagarajan, Nigel P. Topham:
Cooperative Caching for GPUs. ACM Trans. Archit. Code Optim. 13(4): 39:1-39:25 (2016) - [c46]Saumay Dublish, Vijay Nagarajan, Nigel P. Topham:
Characterizing memory bottlenecks in GPGPU workloads. IISWC 2016: 229-230 - 2015
- [c45]Luigi Nardi, Bruno Bodin
, M. Zeeshan Zia, John Mawer, Andy Nisbet, Paul H. J. Kelly, Andrew J. Davison, Mikel Luján, Michael F. P. O'Boyle, Graham D. Riley, Nigel P. Topham, Stephen B. Furber
:
Introducing SLAMBench, a performance and accuracy benchmarking methodology for SLAM. ICRA 2015: 5783-5790 - [c44]Tom Spink
, Harry Wagstaff, Björn Franke
, Nigel P. Topham:
Efficient dual-ISA support in a retargetable, asynchronous Dynamic Binary Translator. SAMOS 2015: 103-112 - 2014
- [c43]Tom Spink
, Harry Wagstaff, Björn Franke
, Nigel P. Topham:
Efficient code generation in a region-based dynamic binary translator. LCTES 2014: 3-12 - [i1]Luigi Nardi, Bruno Bodin, M. Zeeshan Zia, John Mawer, Andy Nisbet, Paul H. J. Kelly, Andrew J. Davison, Mikel Luján, Michael F. P. O'Boyle, Graham D. Riley, Nigel P. Topham, Steve B. Furber:
Introducing SLAMBench, a performance and accuracy benchmarking methodology for SLAM. CoRR abs/1410.2167 (2014) - 2013
- [j9]Oscar Almer, Igor Böhm, Tobias J. K. Edler von Koch, Björn Franke
, Stephen C. Kyle, Volker Seeker, Christopher Thompson, Nigel P. Topham:
A Parallel Dynamic Binary Translator for Efficient Multi-Core Simulation. Int. J. Parallel Program. 41(2): 212-235 (2013) - [j8]Karthik T. Sundararajan, Timothy M. Jones
, Nigel P. Topham:
The Smart Cache: An Energy-Efficient Cache Architecture Through Dynamic Adaptation. Int. J. Parallel Program. 41(2): 305-330 (2013) - [c42]Harry Wagstaff, Miles Gould
, Björn Franke
, Nigel P. Topham:
Early partial evaluation in a JIT-compiled, retargetable instruction set simulator generated from a high-level architecture description. DAC 2013: 21:1-21:6 - [c41]Karthik T. Sundararajan, Timothy M. Jones
, Nigel P. Topham:
RECAP: Region-Aware Cache Partitioning. ICCD 2013: 294-301 - [c40]Christopher Thompson, Miles Gould, Nigel P. Topham:
High speed cycle approximate simulation for cache-incoherent MPSoCs. ICSAMOS 2013: 88-95 - 2012
- [c39]Karthik T. Sundararajan, Timothy M. Jones
, Nigel P. Topham:
Energy-efficient cache partitioning for future CMPs. PACT 2012: 465-466 - [c38]Matthew Bielby, Miles Gould
, Nigel P. Topham:
Design Space Exploration of Hybrid Ultra Low Power Branch Predictors. ARCS 2012: 184-199 - [c37]Marcela Zuluaga, Edwin V. Bonilla, Nigel P. Topham:
Predicting best design trade-offs: A case study in processor customization. DATE 2012: 1030-1035 - [c36]Karthik T. Sundararajan, Vasileios Porpodas, Timothy M. Jones
, Nigel P. Topham, Björn Franke
:
Cooperative partitioning: Energy-efficient cache partitioning for high-performance CMPs. HPCA 2012: 311-322 - [c35]Stephen C. Kyle, Igor Böhm, Björn Franke
, Hugh Leather
, Nigel P. Topham:
Efficiently parallelizing instruction set simulation of embedded multi-core processors using region-based just-in-time dynamic binary translation. LCTES 2012: 21-30 - 2011
- [c34]Oscar Almer, Nigel P. Topham, Björn Franke
:
A Learning-Based Approach to the Automated Design of MPSoC Networks. ARCS 2011: 243-258 - [c33]Karthik T. Sundararajan, Timothy M. Jones
, Nigel P. Topham:
A reconfigurable cache architecture for energy efficiency. Conf. Computing Frontiers 2011: 9 - [c32]Rainer Leupers, Lieven Eeckhout, Grant Martin, Frank Schirrmeister, Nigel P. Topham, Xiaotao Chen:
Virtual Manycore platforms: Moving towards 100+ processor cores. DATE 2011: 715-720 - [c31]Oscar Almer, Miles Gould
, Björn Franke
, Nigel P. Topham:
Selecting the optimal system: automated design of application-specific systems-on-chip. NoCArc@MICRO 2011: 43-50 - [c30]Igor Böhm, Tobias J. K. Edler von Koch, Stephen C. Kyle, Björn Franke
, Nigel P. Topham:
Generalized just-in-time trace compilation using a parallel task farm in a dynamic binary translator. PLDI 2011: 74-85 - [c29]Karthik T. Sundararajan, Timothy M. Jones
, Nigel P. Topham:
Smart cache: A self adaptive cache architecture for energy efficiency. ICSAMOS 2011: 41-50 - [c28]Oscar Almer, Igor Böhm, Tobias J. K. Edler von Koch, Björn Franke
, Stephen C. Kyle, Volker Seeker, Christopher Thompson, Nigel P. Topham:
Scalable multi-core simulation using parallel dynamic binary translation. ICSAMOS 2011: 190-199 - 2010
- [c27]Igor Böhm, Björn Franke
, Nigel P. Topham:
Cycle-accurate performance modelling in an ultra-fast just-in-time dynamic binary translation instruction set simulator. ICSAMOS 2010: 1-10 - [c26]Marcela Zuluaga, Nigel P. Topham:
Exploring the unified design-space of custom-instruction selection and resource sharing. ICSAMOS 2010: 282-291
2000 – 2009
- 2009
- [j7]Marcela Zuluaga, Nigel P. Topham:
Design-Space Exploration of Resource-Sharing Solutions for Custom Instruction Set Extensions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(12): 1788-1801 (2009) - [j6]Alastair Colin Murray, Richard Vincent Bennett, Björn Franke
, Nigel P. Topham:
Code transformation and instruction set extension. ACM Trans. Embed. Comput. Syst. 8(4): 26:1-26:31 (2009) - [c25]Daniel Jones, Nigel P. Topham:
High Speed CPU Simulation Using LTU Dynamic Binary Translation. HiPEAC 2009: 50-64 - [c24]Marcela Zuluaga, Theo Kluter, Philip Brisk, Nigel P. Topham, Paolo Ienne:
Introducing control-flow inclusion to support pipelining in custom instruction set extensions. SASP 2009: 114-121 - 2008
- [c23]Marcela Zuluaga, Nigel P. Topham:
Resource Sharing in Custom Instruction Set Extensions. SASP 2008: 7-13 - 2007
- [c22]Rahman Hassan, Antony Harris, Nigel P. Topham, Aristides Efthymiou
:
Synthetic Trace-Driven Simulation of Cache Memory. AINA Workshops (1) 2007: 764-771 - [c21]Richard Vincent Bennett, Alastair Colin Murray, Björn Franke
, Nigel P. Topham:
Combining source-to-source transformations and processor instruction set extensions for the automated design-space exploration of embedded systems. LCTES 2007: 83-92 - 2003
- [c20]Kar-Lik Wong, Nigel P. Topham:
High performance IDCT realization using complex arithmetic. ICASSP (2) 2003: 313-316 - 2002
- [c19]Kar-Lik Wong, Nigel P. Topham:
OneDSP: A unifying DSP architecture for Systems-on-a-Chip. ICASSP 2002: 3792-3795 - 2000
- [c18]José-Lorenzo Cruz
, Antonio González, Mateo Valero, Nigel P. Topham:
Multiple-banked register file architectures. ISCA 2000: 316-325
1990 – 1999
- 1999
- [j5]Nigel P. Topham, Antonio González
:
Randomized Cache Placement for Eliminating Conflicts. IEEE Trans. Computers 48(2): 185-192 (1999) - [c17]Marcio Merino Fernandes, Josep Llosa, Nigel P. Topham:
Distributed Modulo Scheduling. HPCA 1999: 130-134 - 1998
- [c16]Marcio Merino Fernandes, Josep Llosa
, Nigel P. Topham:
Partitioned Schedules for Clustered VLIW Architectures. IPPS/SPDP 1998: 386-391 - [c15]Nigel P. Topham:
Experiencing quantitative computer architecture. WCAE@ISCA 1998: 15 - 1997
- [c14]Marcio Merino Fernandes, Josep Llosa
, Nigel P. Topham:
Allocating Lifetimes to Queues in Software Pipelined Architectures. Euro-Par 1997: 1066-1073 - [c13]Graham P. Jones, Nigel P. Topham:
A Limitation Study into Access Decoupling. Euro-Par 1997: 1102-1111 - [c12]Antonio González, Mateo Valero, Nigel P. Topham, Joan-Manuel Parcerisa
:
Eliminating Cache Conflict Misses through XOR-Based Placement Functions. International Conference on Supercomputing 1997: 76-83 - [c11]Graham P. Jones, Nigel P. Topham:
A Comparison of Data Prefetching on an Access Decoupled and Superscalar Machine. MICRO 1997: 65-70 - [c10]Nigel P. Topham, Antonio González, José González:
The Design and Performance of a Conflict-Avoiding Cache. MICRO 1997: 71-80 - [c9]Graham P. Jones, Nigel P. Topham:
The Effect of Restricted Instruction Issue Width on an Access Decoupled Architecture. PARCO 1997: 665-672 - 1995
- [j4]Sathiamoorthy Manoharan
, Nigel P. Topham:
An Assessment of Assignment Schemes for Dependency Graphs. Parallel Comput. 21(1): 85-107 (1995) - [c8]Nigel P. Topham, Kenneth McDougall:
Performance of the decoupled ACRI-1 architecture: the perfect club. HPCN Europe 1995: 472-480 - [c7]Nigel P. Topham, Alasdair Rawsthorne, Callum McLean, Muriel Mewissen, Peter L. Bird:
Compiling and Optimizing for Decoupled Architectures. SC 1995: 40 - 1994
- [c6]Sathiamoorthy Manoharan, Nigel P. Topham, A. W. R. Crawford:
Trace-Driven Simulation of Decoupled Architectures. HICSS (1) 1994: 271-279 - 1993
- [c5]Peter L. Bird, Alasdair Rawsthorne, Nigel P. Topham:
The Effectiveness of Decoupling. International Conference on Supercomputing 1993: 47-56 - [c4]T. Harris, Nigel P. Topham:
Performance of Weak Consistency Schemes on the DEC Alpha. PARCO 1993: 429-436 - [c3]Roberto A. Hexsel, Nigel P. Topham:
The Performance of Parallel Loops on SCI-Based Memory Hierarchies. PARCO 1993: 703-706 - 1992
- [c2]Peter L. Bird, Nigel P. Topham, Sathiamoorthy Manoharan
:
A Comparison of Two Memory Models for High Performance Computers. CONPAR 1992: 399-404 - [e1]Nigel P. Topham, Roland N. Ibbett, Thomas Bemmerl:
Programming Environments for Parallel Computing, Proceedings of the IFIP WG 10.3 Workshop on Programming Environments for Parallel Computing, Edinburgh, Scotland, 6-8 April, 1992. IFIP Transactions A-11, North-Holland 1992, ISBN 0-444-89764-X [contents] - 1990
- [j3]Sathiamoorthy Manoharan
, Nigel P. Topham:
A general bound on schedule length for independent tasks. Parallel Comput. 16(1): 69-73 (1990)
1980 – 1989
- 1988
- [j2]Nigel P. Topham, Amos Omondi, Roland N. Ibbett:
On the design and performance of conventional pipelined architectures. J. Supercomput. 1(4): 353-393 (1988) - [j1]Nigel P. Topham, Amos Omondi, Roland N. Ibbett:
Context flow: An alternative to conventional pipelined architectures. J. Supercomput. 2(1): 29-53 (1988) - 1985
- [c1]Roland N. Ibbett, P. C. Capon, Nigel P. Topham:
MU6V: A Parallel Vector Processing System. ISCA 1985: 136-144
Coauthor Index
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