default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDHiPEAC 2009: Paphos, Cyprus
- André Seznec, Joel S. Emer, Michael F. P. O'Boyle, Margaret Martonosi, Theo Ungerer:
High Performance Embedded Architectures and Compilers, Fourth International Conference, HiPEAC 2009, Paphos, Cyprus, January 25-28, 2009. Proceedings. Lecture Notes in Computer Science 5409, Springer 2009, ISBN 978-3-540-92989-5
Invited Program
- Tilak Agerwala:
Keynote: Challenges on the Road to Exascale Computing. 1 - François Bodin:
Keynote: Compilers in the Manycore Era. 2-3
Dynamic Translation and Optimisation
- Mohammad Ansari, Mikel Luján, Christos Kotselidis, Kim Jarvis, Chris C. Kirkham, Ian Watson:
Steal-on-Abort: Improving Transactional Memory Performance through Dynamic Transaction Reordering. 4-18 - Víctor J. Jiménez, Lluís Vilanova
, Isaac Gelado, Marisa Gil, Grigori Fursin, Nacho Navarro:
Predictive Runtime Code Scheduling for Heterogeneous Architectures. 19-33 - Grigori Fursin, Olivier Temam:
Collective Optimization. 34-49 - Daniel Jones, Nigel P. Topham:
High Speed CPU Simulation Using LTU Dynamic Binary Translation. 50-64
Low Level Scheduling
- Mattias V. Eriksson, Christoph W. Kessler:
Integrated Modulo Scheduling for Clustered VLIW Architectures. 65-79 - Mohammed Fellahi, Albert Cohen:
Software Pipelining in Nested Loops with Prolog-Epilog Merging. 80-94 - Martin Thuresson, Magnus Själander, Per Stenström:
A Flexible Code Compression Scheme Using Partitioned Look-Up Tables. 95-109
Parallelism and Resource Control
- Kenzo Van Craeynest, Stijn Eyerman, Lieven Eeckhout:
MLP-Aware Runahead Threads in a Simultaneous Multithreading Processor. 110-124 - Jörg Mische, Sascha Uhrig, Florian Kluge, Theo Ungerer:
IPC Control for Multiple Real-Time Threads on an In-Order SMT Processor. 125-139 - Ghiath Al-Kadi, Andrei Sergeevich Terechko:
A Hardware Task Scheduler for Embedded Video Processing. 140-152 - Frederik Vandeputte, Lieven Eeckhout:
Finding Stress Patterns in Microprocessor Workloads. 153-167
Communication
- Lee W. Howes, Anton Lokhmotov, Alastair F. Donaldson, Paul H. J. Kelly:
Deriving Efficient Data Movement from Decoupled Access/Execute Specifications. 168-182 - Theo Kluter, Philip Brisk, Edoardo Charbon, Paolo Ienne:
MPSoC Design Using Application-Specific Architecturally Visible Communication. 183-197 - Sai Prashanth Muralidhara, Mahmut T. Kandemir:
Communication Based Proactive Link Power Management. 198-215
Mapping for CMPs
- Maik Nijhuis, Herbert Bos, Henri E. Bal, Cédric Augonnet:
Mapping and Synchronizing Streaming Applications on Cell Processors. 216-230 - Yang Ding, Mahmut T. Kandemir, Mary Jane Irwin, Padma Raghavan:
Adapting Application Mapping to Systematic Within-Die Process Variations on Chip Multiprocessors. 231-247 - Major Bhadauria, Vincent M. Weaver, Sally A. McKee:
Accomodating Diversity in CMPs with Heterogeneous Frequencies. 248-262 - Hassan A. Salamy, J. Ramanujam:
A Framework for Task Scheduling and Memory Partitioning for Multi-Processor System-on-Chip. 263-277
Power
- Michael B. Henry, Leyla Nazhandali:
Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT Architecture. 278-292 - Omer Khan, Sandip Kundu:
Predictive Thermal Management for Chip Multiprocessors Using Co-designed Virtual Machines. 293-307 - Suriya Subramanian, Kathryn S. McKinley:
HeDGE: Hybrid Dataflow Graph Execution in the Issue Logic. 308-323 - Muhammad Umar Farooq, Lizy Kurian John, Margarida F. Jacome:
Compiler Controlled Speculation for Power Aware ILP Extraction in Dataflow Architectures. 324-338
Cache Issues
- Matthew A. Watkins, Sally A. McKee, Lambert Schaelicke:
Revisiting Cache Block Superloading. 339-354 - Mohammad Hammoud, Sangyeun Cho, Rami G. Melhem:
ACM: An Efficient Approach for Managing Shared Caches in Chip Multiprocessors. 355-372 - Aditya Yanamandra, Mary Jane Irwin, Vijaykrishnan Narayanan, Mahmut T. Kandemir, Sri Hari Krishna Narayanan:
In-Network Caching for Chip Multiprocessors. 373-388
Parallel Embedded Applications
- Gabriel Falcão Paiva Fernandes, Leonel Sousa, Vítor Manuel Mendes da Silva, José Marinho:
Parallel LDPC Decoding on the Cell/B.E. Processor. 389-403 - Arnaldo Azevedo, Cor Meenderinck, Ben H. H. Juurlink, Andrei Sergeevich Terechko, Jan Hoogerbrugge, Mauricio Alvarez, Alex Ramírez:
Parallel H.264 Decoding on an Embedded Multicore Processor. 404-418
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-02-20 19:46 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
