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2020 – today
- 2024
[c24]Xiu-Yuan Yang, Shen-Li Chen, Ting-En Lin, Hung-Wei Chen, Yi-Mu Lee:
ESD/Latch-up Immunities Enhancements of HV NLDMOSs by the Embedded Discrete SCR/Schottky Alternating Arrangement Design at the Drain Side. ICCE-Taiwan 2024: 783-784- [c23]Ting-En Lin, Shen-Li Chen, Xiu-Yuan Yang, Hung-Wei Chen, Yi-Mu Lee:
Latchup-reliability Impact of High-Voltage nLDMOSs with the Parasitic Schottky Area Modulation in the Source Side. ICCE-Taiwan 2024: 791-792 - 2023
- [c22]Xiu-Yuan Yang, Xing-Chen Mai, Shen-Li Chen, Yu-Jie Chung, Jhong-Yi Lai, Ting-En Lin:
ESD-capability Study of High-voltage nLDMOSs with out the Drift Region DPW Effect. ICCE-Taiwan 2023: 223-224 - [c21]Ting-En Lin, Shen-Li Chen, Zhi-Wei Liu, Xing-Chen Mai, Xiu-Yuan Yang, Yu-Jie Chung:
High-voltage nLDMOS Drain Side Schottky/SCR Modulations for Enhancement Reliability Capabilities. ICCE-Taiwan 2023: 225-226 - 2022
- [c20]Jhong-Yi Lai, Shen-Li Chen, Zhi-Wei Liu, Xing-Chen Mai, Yu-Jie Chung:
ESD Capability Analysis of High-voltage nLDMOSs by the Bulk Terminal Modulation. ICCE-TW 2022: 71-72 - [c19]Zhi-Wei Liu, Shen-Li Chen, Jhong-Yi Lai, Xing-Chen Mai, Yu-Jie Chung:
An Investigation of ESD-Enhancement by the Drain-side Embedded SCR Area Modulation for HV pLDMOSs. ICCE-TW 2022: 73-74 - 2021
- [c18]Shi-Zhe Hong, Shen-Li Chen, Tien-Yu Lan, Yu-Jie Zhou, Zhi-Wei Liu, Jhong-Yi Lai:
ESD-Immunity Impact of HV pLDMOS with Drain-side Embedded Horizontal P-type Schottky Modulations. ICCE-TW 2021: 1-2 - [c17]Tien-Yu Lan, Shen-Li Chen, Yu-Jie Zhou, Shi-Zhe Hong, Jhong-Yi Lai, Zhi-Wei Liu:
Holding-voltage Improvement of UHV Circular nLDMOS Transistors by the Drain-side SCR Engineering. ICCE-TW 2021: 1-2 - [c16]Yu-Jie Zhou, Shen-Li Chen, Tien-Yu Lan, Shi-Zhe Hong, Zhi-Wei Liu, Zhong-Yi Lai:
Improved UHV IGBT-Cell for ESD Protection with High Holding Voltage via a 0.5µm BCD Process. ICCE-TW 2021: 1-2 - 2020
- [c15]Sheng-Kai Fan, Shen-Li Chen, Po-Lin Lin, Shi-Zhe Hong, Tien-Yu Lan, Yu-Jie Zhou:
A Novel SCR-based Schottky Diode and Lightly P-well Additions of HV 60V nLDMOS on ESD Capability. ICCE-TW 2020: 1-2 - [c14]Tien-Yu Lan, Shen-Li Chen, Sheng-Kai Fan, Po-Lin Lin, Yu-Jie Zhou, Shi-Zhe Hong, Hung-Wei Chen:
ESD-capability Influences of UHV Circular nLDMOS Transistors by the Drain-side Ladder-step STI. ICCE-TW 2020: 1-2 - [c13]Po-Lin Lin, Shen-Li Chen, Sheng-Kai Fan, Tien-Yu Lan, Yu-Jie Zhou, Shi-Zhe Hong:
Improving the ESD Robustness of an Ultra-high Voltage nLDMOS Device with the Embedded Schottky Diode. ICCE-TW 2020: 1-2 - [c12]Tien-Yu Lan, Shen-Li Chen, Po-Lin Lin, Sheng-Kai Fan, Yu-Jie Zhou, Shi-Zhe Hong, Hung-Wei Chen:
ESD-ability of Circular nLDMOS Transistors of UHV by Super-junction Length Modulation and Concentration Gradient. ICKII 2020: 57-58 - [c11]Yu-Jie Zhou, Shen-Li Chen, Pei-Lin Wu, Po-Lin Lin, Sheng-Kai Fan, Tien-Yu Lan, Shi-Zhe Hong:
ESD-capability Enhancement of Ultra-high Voltage nLDMOSs by the DPW Discrete Layer. ICKII 2020: 59-60 - [c10]Shi-Zhe Hong, Shen-Li Chen, Sheng-Kai Fan, Po-Lin Lin, Tien-Yu Lan, Yu-Jie Zhou:
Strengthened ESD Reliability of HV nLDMOSs with Embedded Horizontal Schottky Devices. ICKII 2020: 78-79
2010 – 2019
- 2019
- [c9]Sheng-Kai Fan, Shen-Li Chen, Yu-Lin Jhou, Pei-Lin Wu, Po-Lin Lin:
ESD Immunity Impacts of the Drain-Side Heterojunction Device Addition in HV 60 V n/pLDMOS Devices. GCCE 2019: 81-82 - [c8]Po-Lin Lin, Shen-Li Chen, Pei-Lin Wu, Yu-Lin Jhou, Sheng-Kai Fan:
Evaluating the Drift-Region Length Effect of nLDMOS on ESD Ability with a TLP Testing System. GCCE 2019: 83-84 - [c7]Sheng-Kai Fan, Shen-Li Chen, Yu-Lin Jhou, Pei-Lin Wu, Po-Lin Lin:
Channel- & Drift Region's STI-Lengths Impacts of ESD Immunity in HV 60 V nLDMOS Devices. ICCE-TW 2019: 1-2 - [c6]Po-Lin Lin, Shen-Li Chen, Pei-Lin Wu, Yu-Lin Jhou, Sheng-Kai Fan:
ESD-Reliability Investigation 1of an UHV Elliptical LDMOS-SCR by the Drain-Side Junction Replacement. ICCE-TW 2019: 1-2 - 2018
- [j4]Shen-Li Chen, Yu-Ting Huang, Shawn Chang:
Design and Impact on ESD/LU Immunities by Drain-Side Super-Junction Structures in Low-(High-)Voltage MOSFETs for the Power Applications. IEICE Trans. Electron. 101-C(3): 143-150 (2018) - [j3]Shen-Li Chen
, Yi-Cih Wu:
Sensing and Reliability Improvement of Electrostatic-Discharge Transient by Discrete Engineering for High-Voltage 60-V n-Channel Lateral-Diffused MOSFETs with Embedded Silicon-Controlled Rectifiers. Sensors 18(10): 3340 (2018) - 2017
- [j2]Shen-Li Chen, Yu-Ting Huang, Yi-Cih Wu:
Design of High-ESD Reliability in HV Power pLDMOS Transistors by the Drain-Side Isolated SCRs. IEICE Trans. Electron. 100-C(5): 446-452 (2017) - 2016
- [c5]Shen-Li Chen, Yu-Ting Huang, Chih-Ying Yen, Kuei-Jyun Chen, Yi-Cih Wu, Jia-Ming Lin, Chih-Hung Yang:
ESD protection design for the 45-V pLDMOS-SCR (p-n-p-arranged) devices with source-discrete distributions. GCCE 2016: 1-2 - [c4]Shen-Li Chen, Chih-Hung Yang, Chih-Ying Yen, Kuei-Jyun Chen, Yi-Cih Wu, Jia-Ming Lin:
Design on ESD robustness of source-side discrete distribution in the 60-V high-voltage nLDMOS devices. ICCE-TW 2016: 1-2 - 2015
- [j1]Shen-Li Chen:
The I-V Characteristic Prediction of BCD LV pMOSFET Devices Based on an ANFIS-Based Methodology. Adv. Fuzzy Syst. 2015 (2015) - [c3]Shen-Li Chen, Dun-Ying Shu:
By using grey system and Neural-Fuzzy Network methods to obtain the threshold voltage of submicron n-MOSFET DUTs. FSKD 2015: 501-505 - [c2]Shen-Li Chen, Shawn Chang, Yu-Ting Huang, Shun-Bao Chang:
Anti-ESD impacts on 60-V P-channel LDMOS devices as none-ODs zone inserting in the bulk region. ICCE-TW 2015: 266-267 - [c1]Shen-Li Chen, Yu-Ting Huang, Shawn Chang, Shun-Bao Chang:
ESD reliability building in 0.25 μm 60-V p-channel LDMOS DUTs with different embedded SCRs. ICCE-TW 2015: 268-269
Coauthor Index
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