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ORCIDAyan Palchaudhuri
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2020 – today
- 2024
[c15]Ayan Palchaudhuri, Anindya Sundar Dhar:
FPGA Specific Speed-Area Optimized Architectures of Arithmetic Cores with Scan Insertion for Carry Chain Based Multi-level Logic Implementation. VLSID 2024: 617-622- 2022
- [j9]Ayan Palchaudhuri
, Digvijay Anand, Anindya Sundar Dhar:
FPGA fabric conscious architecture design and automation of speed-area efficient Margolus neighborhood based cellular automata with variegated scan path insertion. J. Parallel Distributed Comput. 167: 50-63 (2022) - 2021
- [j8]Ayan Palchaudhuri, Anindya Sundar Dhar:
Speed-area optimized VLSI architecture of multi-bit cellular automaton cell based random number generator on FPGA with testable logic support. J. Parallel Distributed Comput. 151: 13-23 (2021) - [j7]Ayan Palchaudhuri, Sandeep Sharma, Anindya Sundar Dhar:
Design Automation for Tree-based Nearest Neighborhood-aware Placement of High-speed Cellular Automata on FPGA with Scan Path Insertion. ACM Trans. Design Autom. Electr. Syst. 26(4): 31:1-31:34 (2021) - 2020
- [j6]Ayan Palchaudhuri, Anindya Sundar Dhar:
Testable Architecture Design for Programmable Cellular Automata on FPGA Using Run-Time Dynamically Reconfigurable Look-Up Tables. J. Electron. Test. 36(4): 519-536 (2020) - [c14]Ayan Palchaudhuri, Anindya Sundar Dhar:
Primitive Instantiation for Speed-Area Efficient Architecture Design of Cellular Automata based Mageto Logic on FPGA with Built-In Testability. FCCM 2020: 207 - [c13]Ayan Palchaudhuri, Sandeep Sharma, Anindya Sundar Dhar:
Placement Aware Design and Automation of High Speed Architectures for Tree-Structured Linear Cellular Automata on FPGAs with Scan Path Insertion. FPGA 2020: 316
2010 – 2019
- 2019
- [j5]Ayan Palchaudhuri, Anindya Sundar Dhar:
Fault Localization and Testability Approaches for FPGA Fabric Aware Canonic Signed Digit Recoding Implementations. J. Electron. Test. 35(6): 779-796 (2019) - [j4]Ayan Palchaudhuri, Anindya Sundar Dhar:
Design and automation of VLSI architectures for bidirectional scan based fault localization approach in FPGA fabric aware cellular automata topologies. J. Parallel Distributed Comput. 130: 110-125 (2019) - [c12]Ayan Palchaudhuri, Anindya Sundar Dhar:
FPGA Fabric Conscious Design and Implementation of Speed-Area Efficient Signed Digit Add-Subtract Logic through Primitive Instantiation. ACSSC 2019: 1555-1559 - [c11]Ayan Palchaudhuri, Anindya Sundar Dhar:
VLSI Architectures for Jacobi Symbol Computation. VLSID 2019: 335-340 - 2018
- [c10]Ayan Palchaudhuri, Anindya Sundar Dhar:
Fast Carry Chain Based Architectures for Two's Complement to CSD Recoding on FPGAs. ARC 2018: 537-550 - [c9]Ayan Palchaudhuri, Anindya Sundar Dhar:
Redundant Binary to Two's Complement Converter on FPGAs Through Fabric Aware Scan Based Encoding Approach for Fault Localization Support. IPDPS Workshops 2018: 218-221 - [c8]Ayan Palchaudhuri, Anindya Sundar Dhar:
High Speed FPGA Fabric Aware CSD Recoding with Run-Time Support for Fault Localization. VLSID 2018: 186-191 - 2017
- [j3]Ayan Palchaudhuri, Anindya Sundar Dhar:
Built-In Fault Localization Circuitry for High Performance FPGA Based Implementations. J. Electron. Test. 33(4): 529-537 (2017) - [j2]Ayan Palchaudhuri, Amrit Anand Amresh, Anindya Sundar Dhar:
Efficient Automated Implementation of Testable Cellular Automata Based Pseudorandom Generator Circuits on FPGAs. J. Cell. Autom. 12(3-4): 217-247 (2017) - [c7]Ayan Palchaudhuri, Anindya Sundar Dhar:
Redundant Arithmetic Based High Speed Carry Free Hybrid Adders with Built-In Scan Chain on FPGAs. HiPC 2017: 104-113 - [c6]Ayan Palchaudhuri, Anindya Sundar Dhar:
Primitive Instantiation Based Fault Localization Circuitry for High Performance FPGA Designs. VDAT 2017: 594-606 - 2016
- [c5]Ayan Palchaudhuri, Anindya Sundar Dhar:
High performance bit-sliced pipelined comparator tree for FPGAs. VDAT 2016: 1-6 - [c4]Ayan Palchaudhuri, Anindya Sundar Dhar:
Efficient Implementation of Scan Register Insertion on Integer Arithmetic Cores for FPGAs. VLSID 2016: 433-438 - 2015
- [c3]Ayan Palchaudhuri, Rajat Subhra Chakraborty, Durga Prasad Sahoo:
Automated Design of High Performance Integer Arithmetic Cores on FPGA. DSD 2015: 322-329 - [p1]Ayan Palchaudhuri, Rajat Subhra Chakraborty:
A Fabric Component Based Approach to the Architecture and Design Automation of High-Performance Integer Arithmetic Circuits on FPGA. Computational Intelligence in Digital and Network Designs and Applications 2015: 33-68 - 2014
- [c2]Ayan Palchaudhuri, Rajat Subhra Chakraborty, Mohammad Salman, Sreemukh Kardas, Debdeep Mukhopadhyay:
Highly Compact Automated Implementation of Linear CA on FPGAs. ACRI 2014: 388-397 - 2013
- [j1]Rajat Subhra Chakraborty, Indrasish Saha, Ayan Palchaudhuri, Gowtham Kumar Naik:
Hardware Trojan Insertion by Direct Modification of FPGA Configuration Bitstream. IEEE Des. Test 30(2): 45-54 (2013) - 2012
- [c1]Sanjay Burman, Ayan Palchaudhuri, Rajat Subhra Chakraborty, Debdeep Mukhopadhyay, Pranav Singh:
Effect of Malicious Hardware Logic on Circuit Reliability. VDAT 2012: 190-197
Coauthor Index
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