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ORCIDLloyd W. Massengill
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Journal Articles
- 2011
[j5]Nadia Rezzak, Michael L. Alles, Ronald D. Schrimpf
, Sarah Kalemeris, Lloyd W. Massengill, John Sochacki, Hugh J. Barnaby:
The sensitivity of radiation-induced leakage to STI topology and sidewall doping. Microelectron. Reliab. 51(5): 889-894 (2011)- 2008
- [j4]Patrick R. Fleming, Brian D. Olson, W. Timothy Holman, Bharat L. Bhuva, Lloyd W. Massengill:
Design Technique for Mitigation of Soft Errors in Differential Switched-Capacitor Circuits. IEEE Trans. Circuits Syst. II Express Briefs 55-II(9): 838-842 (2008) - 1992
- [j3]Lloyd W. Massengill, David Bryan Mundie:
An analog neural hardware implementation using charge-injection multipliers and neutron-specific gain control. IEEE Trans. Neural Networks 3(3): 354-362 (1992) - 1991
- [j2]David Bryan Mundie, Lloyd W. Massengill:
Weight decay and resolution effects in feedforward artificial neural networks. IEEE Trans. Neural Networks 2(1): 168-170 (1991) - 1989
- [j1]Lloyd W. Massengill, Neal Bengtson:
RSIM: A circuit simulation program for VLSI interconnect networks. Simul. 52(2): 68-77 (1989)
Conference and Workshop Papers
- 2021
- [c8]Yoni Xiong, Alexandra Feeley, Lloyd W. Massengill, Bharat L. Bhuva, Shi-Jie Wen, Rita Fung:
Frequency, LET, and Supply Voltage Dependence of Logic Soft Errors at the 7-nm Node. IRPS 2021: 1-5 - 2020
- [c7]Jingchen Cao, Lyuan Xu, Shi-Jie Wen, Rita Fung, Balaji Narasimham, Lloyd W. Massengill, Bharat L. Bhuva:
Temperature Dependence of Single-Event Transient Pulse Widths for 7-nm Bulk FinFET Technology. IRPS 2020: 1-5 - 2019
- [c6]Jingchen Cao, Lyuan Xu, Bharat L. Bhuva, Shi-Jie Wen, Richard Wong, Balaji Narasimham, Lloyd W. Massengill:
Alpha Particle Soft-Error Rates for D-FF Designs in 16-Nm and 7-Nm Bulk FinFET Technologies. IRPS 2019: 1-5 - [c5]Lyuan Xu, Jingchen Cao, Bharat L. Bhuva, Indranil Chatterjee, Shi-Jie Wen, Richard Wong, Lloyd W. Massengill:
Single-Event Upset Responses of Dual- and Triple-Well D Flip-Flop Designs in 7-nm Bulk FinFET Technology. IRPS 2019: 1-5 - 2018
- [c4]H. Zhang, H. Jiang, M. R. Eaker, Kurt J. Lezon, Balaji Narasimham, Nihaar N. Mahatme, Lloyd W. Massengill, Bharat L. Bhuva:
Evaluation on flip-flop physical unclonable functions in a 14/16-nm bulk FinFET technology. IRPS 2018: 1 - [c3]Hui Jiang, H. Zhang, R. C. Harrington, J. A. Maharrey, J. S. Kauppila, Lloyd W. Massengill, Bharat L. Bhuva:
Impact of supply voltage and particle LET on the soft error rate of logic circuits. IRPS 2018: 4 - [c2]H. Jiang, H. Zhang, Balaji Narasimham, Lloyd W. Massengill, Bharat L. Bhuva:
Designing soft-error-aware circuits with power and speed optimization. IRPS 2018: 5-1 - 2015
- [c1]N. Tam, Bharat L. Bhuva, Lloyd W. Massengill, Dennis R. Ball, Michael W. McCurdy, Michael L. Alles, Indranil Chatterjee:
Multi-cell soft errors at the 16-nm FinFET technology node. IRPS 2015: 4
Coauthor Index
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