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Publication search results
found 45 matches
- 2008
- Mehmet Fatih Akay, Constantine Katsinis:
Contention resolution on a broadcast-based distributed shared memory multiprocessor. IET Comput. Digit. Tech. 2(1): 45-55 (2008) - Ahmad A. Al-Yamani, Narendra Devta-Prasanna, Arun Gunda:
Comparative study of centralised and distributed compatibility-based test data compression. IET Comput. Digit. Tech. 2(2): 108-117 (2008) - Kashif Ali, Mokhtar Aboelaze, Suprakash Datta:
Energy efficient i-cache using multiple line buffers with prediction. IET Comput. Digit. Tech. 2(5): 355-362 (2008) - Daniel A. Andersson, Lars J. Svensson, Per Larsson-Edefors:
Time-domain interconnect characterisation flow for appropriate model segmentation. IET Comput. Digit. Tech. 2(4): 265-274 (2008) - Jun Ho Bahn, Nader Bagherzadeh:
Design of simulation and analytical models for a 2D-meshed asymmetric adaptive router. IET Comput. Digit. Tech. 2(1): 63-73 (2008) - Tomas Bengtsson, Shashi Kumar, Raimund Ubar, Artur Jutman, Zebo Peng:
Test methods for crosstalk-induced delay and glitch faults in network-on-chip interconnects implementing asynchronous communication protocols. IET Comput. Digit. Tech. 2(6): 445-460 (2008) - Andrew Byrne, Emanuel M. Popovici, William P. Marnane:
Versatile processor for GF(pm) arithmetic for use in cryptographic applications. IET Comput. Digit. Tech. 2(4): 253-264 (2008) - Kuei-Chung Chang, Tien-Fu Chen:
Low-power algorithm for automatic topology generation for application-specific networks on chips. IET Comput. Digit. Tech. 2(3): 239-249 (2008) - Vikas Chaudhary, Tai-Hua Chen, F. Sheerin, Lawrence T. Clark:
Critical race-free low-power nand match line content addressable memory tagged cache memory. IET Comput. Digit. Tech. 2(1): 40-44 (2008) - Aiman H. El-Maleh:
Test data compression for system-on-a-chip using extended frequency-directed run-length code. IET Comput. Digit. Tech. 2(3): 155-163 (2008) - Aiman H. El-Maleh:
Efficient test compression technique based on block merging. IET Comput. Digit. Tech. 2(5): 327-335 (2008) - Yucheng Feng, W. Zheng, Matt Francis, H. Alan Mantooth:
Model order reduction by Miller's theorem and root localisation. IET Comput. Digit. Tech. 2(5): 363-376 (2008) - Kanupriya Gulati, Mandar Waghmode, Sunil P. Khatri, Weiping Shi:
Efficient, scalable hardware engine for Boolean satisfiability and unsatisfiable core extraction. IET Comput. Digit. Tech. 2(3): 214-229 (2008) - Kenny Johansson, Oscar Gustafsson, Lars Wanhammar:
Implementation of elementary functions for logarithmic number systems. IET Comput. Digit. Tech. 2(4): 295-304 (2008) - John A. Kalomiros, John N. Lygouras:
Hardware implementation of a stereo co-processor in a medium-scale field programmable gate array. IET Comput. Digit. Tech. 2(5): 336-346 (2008) - Chi-Chou Kao:
Computer-aided crosstalk minimisation design for system-on-chip. IET Comput. Digit. Tech. 2(1): 23-29 (2008) - Daniel Karlsson, Petru Eles, Zebo Peng:
Model validation for embedded systems using formal method-aided simulation. IET Comput. Digit. Tech. 2(6): 413-433 (2008) - Per Karlström, Andreas Ehliar, Dake Liu:
High-performance, low-latency field-programmable gate array-based floating-point adder and multiplier units in a Virtex 4. IET Comput. Digit. Tech. 2(4): 305-313 (2008) - Ari Kulmala, Erno Salminen, Timo D. Hämäläinen:
Distributed bus arbitration algorithm comparison on FPGA-based MPEG-4 multiprocessor system on chip. IET Comput. Digit. Tech. 2(4): 314-325 (2008) - Jong Wook Kwak, Chu Shik Jhon:
High-performance embedded branch predictor by combining branch direction history and global branch history. IET Comput. Digit. Tech. 2(2): 142-154 (2008) - Erik Larsson:
Architecture for integrated test data compression and abort-on-fail testing in a multi-site environment. IET Comput. Digit. Tech. 2(4): 275-284 (2008) - H.-T. Lin, J. C.-M. Li:
Simultaneous capture and shift power reduction test pattern generator for scan testing. IET Comput. Digit. Tech. 2(2): 132-141 (2008) - César Augusto Missio Marcon, Edson Ifarraguirre Moreno, Ney Laert Vilar Calazans, Fernando Gehm Moraes:
Comparison of network-on-chip mapping algorithms targeting low energy consumption. IET Comput. Digit. Tech. 2(6): 471-482 (2008) - Muhammad N. Marsono, M. Watheq El-Kharashi, Fayez Gebali:
Binary LNS-based naive Bayes inference engine for spam control: noise analysis and FPGA implementation. IET Comput. Digit. Tech. 2(1): 56-62 (2008) - Brad Matthews, Itamar Elhanany:
Hardware architecture for high-speed real-time dynamic programming applications. IET Comput. Digit. Tech. 2(3): 164-171 (2008) - Saraju P. Mohanty, Elias Kougianos, Dhiraj K. Pradhan:
Simultaneous scheduling and binding for low gate leakage nano-complementary metaloxide-semiconductor data path circuit behavioural synthesis. IET Comput. Digit. Tech. 2(2): 118-131 (2008) - José L. Núñez-Yáñez, Doug A. Edwards, Antonio Marcello Coppola:
Adaptive routing strategies for fault-tolerant on-chip networks in dynamically reconfigurable systems. IET Comput. Digit. Tech. 2(3): 184-198 (2008) - César Pedraza, Javier Castillo, José Ignacio Martínez, Pablo Huerta, Carlos S. de La Lama:
Self-reconfigurable secure file system for embedded Linux. IET Comput. Digit. Tech. 2(6): 461-470 (2008) - Silvia Del Pino, Daniel Chaver, Luis Piñuel, Manuel Prieto, Francisco Tirado:
Energy reduction of the fetch mechanism through dynamic adaptation. IET Comput. Digit. Tech. 2(2): 94-107 (2008) - Fredy Rivera, Marcos Sánchez-Élez, Román Hermida, Nader Bagherzadeh:
Scheduling methodology for conditional execution of kernels onto multicontext reconfigurable architectures. IET Comput. Digit. Tech. 2(3): 199-213 (2008)
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retrieved on 2024-06-30 02:45 CEST from data curated by the dblp team
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