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2020 – today
- 2024
[j5]Luca Valente
, Alessandro Nadalini, Asif Hussain Chiralil Veeran, Mattia Sinigaglia, Bruno Sá, Nils Wistoff, Yvan Tortorella, Simone Benatti, Rafail Psiakis, Ari Kulmala, Baker Mohammad, Sandro Pinto, Daniele Palossi, Luca Benini, Davide Rossi:
A Heterogeneous RISC-V Based SoC for Secure Nano-UAV Navigation. IEEE Trans. Circuits Syst. I Regul. Pap. 71(5): 2266-2279 (2024)- [i2]Luca Valente, Alessandro Nadalini, Asif Veeran, Mattia Sinigaglia, Bruno Sá, Nils Wistoff, Yvan Tortorella, Simone Benatti, Rafail Psiakis, Ari Kulmala, Baker Mohammad, Sandro Pinto, Daniele Palossi, Luca Benini, Davide Rossi:
A Heterogeneous RISC-V based SoC for Secure Nano-UAV Navigation. CoRR abs/2401.03531 (2024) - [i1]Maicol Ciani, Emanuele Parisi, Alberto Musa, Francesco Barchi, Andrea Bartolini, Ari Kulmala, Rafail Psiakis, Angelo Garofalo, Andrea Acquaviva, Davide Rossi:
Unleashing OpenTitan's Potential: a Silicon-Ready Embedded Secure Element for Root of Trust and Cryptographic Offloading. CoRR abs/2406.11558 (2024) - 2023
- [c19]Luca Valente, Asif Veeran, Mattia Sinigaglia, Yvan Tortorella, Alessandro Nadalini, Nils Wistoff, Bruno Sá, Angelo Garofalo, Rafail Psiakis, M. Tolba, Ari Kulmala, Nimisha Limaye, Ozgur Sinanoglu, Sandro Pinto, Daniele Palossi, Luca Benini, Baker Mohammad, Davide Rossi:
Shaheen: An Open, Secure, and Scalable RV64 SoC for Autonomous Nano-UAVs. HCS 2023: 1-12 - [c18]Pegdwende Romaric Nikiema, Alessandro Palumbo, Allan Aasma, Luca Cassano, Angeliki Kritikakou, Ari Kulmala, Jari Lukkarila, Marco Ottavi, Rafail Psiakis, Marcello Traiola:
Towards Dependable RISC-V Cores for Edge Computing Devices. IOLTS 2023: 1-7 - 2022
- [c17]Antti Rautakoura, Timo Hämäläinen, Ari Kulmala, Tero Lehtinen, Mehdi Duman, Mohamed Ibrahim:
Ballast: Implementation of a Large MP-SoC on 22nm ASIC Technology. DSD 2022: 276-283
2010 – 2019
- 2019
- [j4]Markku Vajaranta, Arto Oinonen, Timo D. Hämäläinen, Vili Viitamäki, Jouni Markunmäki, Ari Kulmala:
Feasibility of FPGA accelerated IPsec on cloud. Microprocess. Microsystems 71 (2019) - 2018
- [c16]Markku Vajaranta, Vili Viitamäki, Arto Oinonen, Timo D. Hämäläinen, Ari Kulmala, Jouni Markunmäki:
Feasibility of FPGA Accelerated IPsec on Cloud. DSD 2018: 569-572 - [c15]Marko Viitanen, Jarno Vanne, Timo D. Hämäläinen, Ari Kulmala:
Low Latency Edge Rendering Scheme for Interactive 360 Degree Virtual Reality Gaming. ICDCS 2018: 1557-1560 - [c14]Panu Sjövall, Vili Viitamäki, Jarno Vanne, Timo D. Hämäläinen, Ari Kulmala:
FPGA-Powered 4K120p HEVC Intra Encoder. ISCAS 2018: 1-5 - [c13]Vili Viitamäki, Panu Sjövall, Jarno Vanne, Timo D. Hämäläinen, Ari Kulmala:
Live Demonstration: 4K100p HEVC Intra Encoder. ISCAS 2018: 1- - 2017
- [c12]Panu Sjovall, Vili Viitamäki, Arto Oinonen, Jarno Vanne, Timo D. Hämäläinen, Ari Kulmala:
Kvazaar 4K HEVC intra encoder on FPGA accelerated airframe server. SiPS 2017: 1-6
2000 – 2009
- 2009
- [b1]Ari Kulmala:
Scalable multiprocessor system-on-chip architecture design on FPGA. University of Tampere, Finland, 2009 - [j3]Ari Kulmala, Erno Salminen, Marko Hännikäinen, Timo D. Hämäläinen:
Evaluating SoC Network Performance in MPEG-4 Encoder. J. Signal Process. Syst. 56(2-3): 105-123 (2009) - 2008
- [j2]Ari Kulmala, Erno Salminen, Timo D. Hämäläinen:
Distributed bus arbitration algorithm comparison on FPGA-based MPEG-4 multiprocessor system on chip. IET Comput. Digit. Tech. 2(4): 314-325 (2008) - [c11]Erno Salminen, Ari Kulmala, Timo Hämäläinen:
On the credibility of load-latency measurement of network-on-chips. SoC 2008: 1-7 - 2007
- [c10]Ari Kulmala, Erno Salminen, Timo D. Hämäläinen:
Instruction Memory Architecture Evaluation on Multiprocessor FPGA MPEG-4 Encoder. DDECS 2007: 105-110 - [c9]Antti Rasmus, Ari Kulmala, Erno Salminen, Timo D. Hämäläinen:
IP Integration Overhead Analysis in System-on-Chip Video Encoder. DDECS 2007: 333-336 - [c8]Erno Salminen, Ari Kulmala, Timo D. Hämäläinen:
On network-on-chip comparison. DSD 2007: 503-510 - [c7]Ari Kulmala, Erno Salminen, Timo D. Hämäläinen:
Evaluating Large System-on-Chip on Multi-FPGA Platform. SAMOS 2007: 179-189 - 2006
- [j1]Ari Kulmala, Olli Lehtoranta, Timo D. Hämäläinen, Marko Hännikäinen:
Scalable MPEG-4 Encoder on FPGA Multiprocessor SOC. EURASIP J. Embed. Syst. 2006 (2006) - [c6]Ari Kulmala, Erno Salminen, Olli Lehtoranta, Timo D. Hämäläinen, Marko Hännikäinen:
Impact of Shared Instruction Memory on Performance of FPGA-based MP-SoC Video Encoder. DDECS 2006: 59-64 - [c5]Ari Kulmala, Timo D. Hämäläinen, Marko Hännikäinen:
Comparison of GALS and Synchronous Architectures with MPEG-4 Video Encoder on Multiprocessor System-on-Chip FPGA. DSD 2006: 83-88 - [c4]Ari Kulmala, Timo D. Hämäläinen, Marko Hännikäinen:
Reliable GALS Implementation of MPEG-4 Encoder with Mixed Clock FIFO on Standard FPGA. FPL 2006: 1-6 - [c3]Ari Kulmala, Erno Salminen, Marko Hännikäinen, Timo D. Hämäläinen:
Evaluating SoC Network Performance in MPEG-4 Encoder. SiPS 2006: 250-255 - 2005
- [c2]Olli Lehtoranta, Erno Salminen, Ari Kulmala, Marko Hännikäinen, Timo D. Hämäläinen:
A Parallel MPEG-4 Encoder for FPGA Based Multiprocessor SoC. FPL 2005: 380-385 - [c1]Erno Salminen, Ari Kulmala, Timo D. Hämäläinen:
HIBI-based multiprocessor SoC on FPGA. ISCAS (4) 2005: 3351-3354
Coauthor Index
aka: Timo D. Hämäläinen
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