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ORCIDVili Viitamäki
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- affiliation: Tampere University of Technology, Laboratory of Pervasive Computing, Finland
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2010 – 2019
- 2019
[j1]Markku Vajaranta, Arto Oinonen
, Timo D. Hämäläinen, Vili Viitamäki, Jouni Markunmäki, Ari Kulmala:
Feasibility of FPGA accelerated IPsec on cloud. Microprocess. Microsystems 71 (2019)- 2018
- [c6]Markku Vajaranta, Vili Viitamäki, Arto Oinonen, Timo D. Hämäläinen, Ari Kulmala, Jouni Markunmäki:
Feasibility of FPGA Accelerated IPsec on Cloud. DSD 2018: 569-572 - [c5]Panu Sjövall, Vili Viitamäki, Jarno Vanne, Timo D. Hämäläinen, Ari Kulmala:
FPGA-Powered 4K120p HEVC Intra Encoder. ISCAS 2018: 1-5 - [c4]Vili Viitamäki, Panu Sjövall, Jarno Vanne, Timo D. Hämäläinen, Ari Kulmala:
Live Demonstration: 4K100p HEVC Intra Encoder. ISCAS 2018: 1- - 2017
- [c3]Panu Sjovall, Vili Viitamäki, Jarno Vanne, Timo D. Hämäläinen:
High-level synthesis implementation of HEVC 2-D DCT/DST on FPGA. ICASSP 2017: 1547-1551 - [c2]Vili Viitamäki, Panu Sjovall, Jarno Vanne, Timo D. Hämäläinen:
High-level synthesized 2-D IDCT/IDST implementation for HEVC codecs on FPGA. ISCAS 2017: 1-4 - [c1]Panu Sjovall, Vili Viitamäki, Arto Oinonen, Jarno Vanne, Timo D. Hämäläinen, Ari Kulmala:
Kvazaar 4K HEVC intra encoder on FPGA accelerated airframe server. SiPS 2017: 1-6
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