- 2014
- Kaveh Aasaraai, Andreas Moshovos:
What limits the operating frequency of a soft processor design. ReConFig 2014: 1-6 - Cristinel Ababei, Rajesh G. Kavasseri
, Mohammad A. Zare:
Net reordering and multicommodity flow based global routing for FPGAs. ReConFig 2014: 1-6 - Vignesh Adhinarayanan, Thaddeus Koehn, Krzysztof Kepa, Wu-chun Feng, Peter Athanas:
On the performance and energy efficiency of FPGAs and GPUs for polyphase channelization. ReConFig 2014: 1-7 - Khaled E. Ahmed, Mohammed M. Farag:
Overloaded CDMA bus topology for MPSoC interconnect. ReConFig 2014: 1-7 - Karim M. A. Ali, Rabie Ben Atitallah, Saïd Hanafi, Jean-Luc Dekeyser:
A generic pixel distribution architecture for parallel video processing. ReConFig 2014: 1-8 - Rico Backasch, Gerald Hempel, Stefan Werner, Sven Groppe, Thilo Pionteck:
Identifying homogenous reconfigurable regions in heterogeneous FPGAs for module relocation. ReConFig 2014: 1-6 - Poona Bahrebar, Dirk Stroobandt:
Adaptive and reconfigurable fault-tolerant routing method for 2D Networks-on-Chip. ReConFig 2014: 1-8 - Yu Bai, Mingjie Lin:
Stochastically computing discrete Fourier transform with reconfigurable digital fabric. ReConFig 2014: 1-7 - Adrien Blanchardon, Roselyne Chotin-Avot, Habib Mehrez, Emna Amouri:
Impact of defect tolerance techniques on the criticality of a SRAM-based mesh of cluster FPGA. ReConFig 2014: 1-6 - Timm Bostelmann, Sergei Sawitzki:
A conceptual toolchain for an application domain specific reconfigurable logic architecture. ReConFig 2014: 1-4 - Gang Chen, Biao Hu, Kai Huang, Alois C. Knoll, Kai Huang, Di Liu, Todor P. Stefanov:
Automatic cache partitioning and time-triggered scheduling for real-time MPSoCs. ReConFig 2014: 1-8 - Chuan Cheng, Christos-Savvas Bouganis:
Memory optimisation for hardware induction of axis-parallel decision tree. ReConFig 2014: 1-5 - Tom Davidson, Dirk Stroobandt:
Data path analysis for dynamic circuit specialisation. ReConFig 2014: 1-8 - James Demma, Peter Athanas:
A hardware generator for factor graph applications. ReConFig 2014: 1-8 - Hongyuan Ding, Miaoqing Huang:
A unified OpenCL-flavor programming model with scalable hybrid hardware platform on FPGAs. ReConFig 2014: 1-7 - Tomas Drahonovsky, Martin Rozkovec, Ondrej Novák:
A highly flexible reconfigurable system on a Xilinx FPGA. ReConFig 2014: 1-6 - Rui Policarpo Duarte, Christos-Savvas Bouganis:
Zero-latency datapath error correction framework for over-clocking DSP applications on FPGAs. ReConFig 2014: 1-7 - Viet Vu Duy, Oliver Sander, Timo Sandmann, Steffen Bähr, Jan Heidelberger, Jürgen Becker:
Enabling partial reconfiguration for coprocessors in mixed criticality multicore systems using PCI express single-root I/O virtualization. ReConFig 2014: 1-6 - Jorge Echavarria, Alicia Morales-Reyes, René Cumplido, Miguel A. Salido:
FSM merging and reduction for IP cores watermarking using Genetic Algorithms. ReConFig 2014: 1-7 - Andreas Emeretlis, George Theodoridis, George-Othon Glentis:
High-performance FPGA implementations of volterra DFEs for optical fiber systems. ReConFig 2014: 1-8 - Maik Ender, Gerd Duppmann, Alexander Wild, Thomas Pöppelmann, Tim Güneysu:
A hardware-assisted proof-of-concept for secure VoIP clients on untrusted operating systems. ReConFig 2014: 1-6 - Alfredo Espinoza-Rhoton, Luis F. Gonzalez-Perez, J. L. Ponce, Borrayo-S. Hector, Lennin C. Yllescas-Calderon, Ramón Parra-Michel, Hassan Aboushady:
An FPGA-based all-digital 802.11b & 802.15.4 receiver for the Software Defined Radio paradigm. ReConFig 2014: 1-6 - Mohammed M. Farag, Mohammad A. Ewais:
Smart employment of circuit redundancy to effectively counter trojans (SECRET) in third-party IP cores. ReConFig 2014: 1-6 - Alexander Fell, Zoltán Endre Rákossy, Anupam Chattopadhyay:
Force-directed scheduling for Data Flow Graph mapping on Coarse-Grained Reconfigurable Architectures. ReConFig 2014: 1-8 - Felipe A. P. de Figueiredo, Fabiano S. Mathilde, Fabbryccio A. C. M. Cardoso, Rafael M. Vilela, Joao Paulo Miranda:
Efficient FPGA-based implementation of a CAZAC sequence generator for 3GPP LTE. ReConFig 2014: 1-6 - Thomas P. Flatley:
Keynote - SpaceCube - A family of reconfigurable hybrid on-board science data processors. ReConFig 2014: 1-2 - Naoyuki Fujita, Toshifumi Yanagisawa, Hirohisa Kurosaki, Hiroshi Oda:
The speed-up of detection of space debris using "InterP" and "FLOPS2D". ReConFig 2014: 1-6 - Vaibhav R. Gandhi, Yun Rock Qu, Viktor K. Prasanna:
High-throughput hash-based online traffic classification engines on FPGA. ReConFig 2014: 1-6 - Shanyuan Gao, Jeremy Chritz:
Characterization of OpenCL on a scalable FPGA architecture. ReConFig 2014: 1-6 - Jan Gray:
Keynote - The past and future of FPGA soft processors. ReConFig 2014: 1
