- 2010
- Gaurav Ajwani, Chris Chu, Wai-Kei Mak:
FOARS: FLUTE based obstacle-avoiding rectilinear steiner tree construction. ISPD 2010: 27-34 - Charles J. Alpert, Zhuo Li, Michael D. Moffitt, Gi-Joon Nam, Jarrod A. Roy, Gustavo E. Téllez:
What makes a design difficult to route. ISPD 2010: 7-12 - Yongchan Ban, Savithri Sundareswaran, David Z. Pan:
Total sensitivity based dfm optimization of standard library cells. ISPD 2010: 113-120 - Ashutosh Chakraborty, David Z. Pan:
Skew management of NBTI impacted gated clock trees. ISPD 2010: 127-133 - Huang-Yu Chen, Szu-Jui Chou, Yao-Wen Chang
:
Density gradient minimization with coupling-constrained dummy fill for CMP control. ISPD 2010: 105-111 - Jason Cong, Guojie Luo:
An analytical placer for mixed-size 3D placement. ISPD 2010: 61-66 - Michael Eick, Martin Strasser, Helmut E. Graeb, Ulf Schlichtmann:
Automatic generation of hierarchical placement rules for analog integrated circuits. ISPD 2010: 47-54 - Vassilios Gerousis:
Physical design implementation for 3D IC: methodology and tools. ISPD 2010: 57 - Patrick Groeneveld:
Going with the flow: bridging the gap between theory and practice in physical design. ISPD 2010: 3 - Mar Hershenson:
Design platform for electrical and physical co-design of analog circuits. ISPD 2010: 45 - Jin Hu, Jarrod A. Roy, Igor L. Markov:
Completing high-quality global routes. ISPD 2010: 35-41 - Tsung-Wei Huang, Tsung-Yi Ho:
A two-stage ILP-based droplet routing algorithm for pin-constrained digital microfluidic biochips. ISPD 2010: 201-208 - Iris Hui-Ru Jiang, Hua-Yu Chang, Chih-Long Chang:
Optimal wiring topology for electromigration avoidance considering multiple layers and obstacles. ISPD 2010: 177-184 - Neeraj Kaul:
Design planning trends and challenges. ISPD 2010: 5 - Serge Leef:
Challenges and opportunities in optimization of automotive electronics. ISPD 2010: 15 - Zhuo Li, David A. Papa, Charles J. Alpert, Shiyan Hu, Weiping Shi, Cliff C. N. Sze, Nancy Ying Zhou:
Ultra-fast interconnect driven cell cloning for minimizing critical path delay. ISPD 2010: 75-82 - Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly:
Performance study of VeSFET-based, high-density regular circuits. ISPD 2010: 161-168 - Lijuan Luo, Tan Yan, Qiang Ma, Martin D. F. Wong, Toshiyuki Shibuya:
B-escape: a simultaneous escape routing algorithm based on boundary routing. ISPD 2010: 19-25 - Venkata Rajesh Mekala, Yifang Liu, Xiaoji Ye, Jiang Hu, Peng Li:
Accurate clock mesh sizing via sequential quadraticprogramming. ISPD 2010: 135-142 - Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer:
Interconnect power and delay optimization by dynamic programming in gridded design rules. ISPD 2010: 153-160 - Sani R. Nassif, Kevin J. Nowka:
Physical design challenges beyond the 22nm node. ISPD 2010: 13-14 - John Park:
Thinking outside of the chip. ISPD 2010: 17 - Rob A. Rutenbar:
Analog layout synthesis: what's missing? ISPD 2010: 43 - Sachin S. Sapatnekar:
Adding a new dimension to physical design. ISPD 2010: 55 - Louis Scheffer:
Physical design of biological systems. ISPD 2010: 1 - Rupesh S. Shelar, Marek Patyra:
Impact of local interconnects on timing and power in a high performance microprocessor. ISPD 2010: 145-152 - Cliff C. N. Sze:
ISPD 2010 high performance clock network synthesis contest: benchmark suite and results. ISPD 2010: 143 - Zongwu Tang:
Efficient design practices for thermal management of a TSV based 3D IC system. ISPD 2010: 59 - Natarajan Viswanathan, Gi-Joon Nam, Jarrod A. Roy, Zhuo Li, Charles J. Alpert, Shyam Ramji, Chris Chu:
ITOP: integrating timing optimization within placement. ISPD 2010: 83-90 - Renshen Wang, Evangeline F. Y. Young, Ronald L. Graham, Chung-Kuan Cheng:
Physical synthesis of bus matrix for high bandwidth low power on-chip communications. ISPD 2010: 91-96
