- 1997
- Chouki Aktouf, Ghassan Al Hayek, Chantal Robach:
Concurrent testing of VLSI digital signal processors using mutation based testing. DFT 1997: 94-99 - Gerard A. Allan, Anthony J. Walton:
Efficient critical area estimation for arbitrary defect shapes. DFT 1997: 20-28 - Anna Antola, Vincenzo Piuri, Mariagiovanna Sami:
Semi-Concurrent Error Detection in Data Paths. DFT 1997: 298-306 - David Ashen, Fred J. Meyer, Nohpill Park, Fabrizio Lombardi:
Testing of programmable logic devices (PLD) with faulty resources. DFT 1997: 76-84 - Alfredo Benso, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
, Jaan Raik, Raimund Ubar:
Exploiting High-Level Descriptions for Circuits Fault Tolerance Assessments. DFT 1997: 212-217 - Pascal Bichebois, Pierre Mathery:
Analysis of Defect to Yield Correlation on Memories: Method, Algorithms and Limits. DFT 1997: 44-52 - Cristiana Bolchini, Giacomo Buonanno, M. Cozzini, Donatella Sciuto, Renato Stefanelli:
Designing Ad-Hoc Codes for the Realization of Fault Tolerant CMOS Networks. DFT 1997: 204-211 - Cristiana Bolchini, Donatella Sciuto, Fabio Salice:
Designing Networks with Error Detection Properties through the Fault-Error Relation. DFT 1997: 290-297 - Zhan Chen, Israel Koren:
Crosstalk Minimization in Three-Layer HVH Channel Routing. DFT 1997: 38-43 - Fausto Distante, Mariagiovanna Sami, Renato Stefanelli:
Harvesting Through Array Partitioning: A Solution to Achieve Defect Tolerance. DFT 1997: 261-271 - Michele Favalli, Cecilia Metra:
Low-level error recovery mechanism for self-checking sequential circuits. DFT 1997: 234-242 - Fabrizio Ferrandi, Franco Fummi, Laura Pozzi, Mariagiovanna Sami:
Configuration-Specific Test Pattern Extraction for Field Programmable Gate Arrays. DFT 1997: 85-93 - Yves Gagnon, Yvon Savaria, Michel Meunier, Claude Thibeault:
Are defect-tolerant circuits with redundancy really cost-effective? Complete and realistic cost model. DFT 1997: 157-165 - W. Lynn Gallagher, Earl E. Swartzlander Jr.:
Fast Error-Correcting Newton-Raphson Dividers Using Time Shared TMR. DFT 1997: 243-251 - Anil Gandhi, Stacy Hall, Ron Harris:
An examination of empirically derived within-die local probabilities of failure. DFT 1997: 53-61 - Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira:
Realistic Fault Extraction for High-Quality Design and Test of VLSI Systems. DFT 1997: 29-37 - Michael Gössel, Sebastian T. J. Fenn, David Taylor:
On-line error detection for finite field multipliers. DFT 1997: 307-312 - Yu-Yau Guo, Jien-Chung Lo, Cecilia Metra:
Fast and area-time efficient Berger code checkers. DFT 1997: 110-118 - Wei Liang Huang, Fred J. Meyer, Fabrizio Lombardi:
Multiple fault detection in logic resources of FPGAs. DFT 1997: 186-194 - Michel Kafrouni, Claude Thibeault, Yvon Savaria:
A Cost Model for VLSI / MCM Systems. DFT 1997: 148-156 - Xrysovalantis Kavousianos, Dimitris Nikolos, G. Sidiropoulos:
Design of Compact and High speed, Totally Self Checking CMOS Checkers for m-out-of-n Codes. DFT 1997: 128-136 - Christopher G. Knight, Adit D. Singh, Victor P. Nelson:
An IDDQ Sensor for Concurrent Timing Error Detection. DFT 1997: 281-289 - Israel Koren, Zahava Koren:
Analysis of a Hybrid Defect-Tolerance Scheme for High-Density Memory ICs. DFT 1997: 166-174 - Sandra Levasseur, Frederic Duvivier:
Application of a yield model merging critical areas and defectivity to industrial products. DFT 1997: 11-19 - Cecilia Metra, Michele Favalli, Bruno Riccò:
Compact and low power on-line self-testing voting scheme. DFT 1997: 137-147 - Stanislaw J. Piestrak:
Design of encoders and self-testing checkers for some systematic unidirectional error detecting codes. DFT 1997: 119-127 - Witold A. Pleskacz, Wojciech Maly:
Improved Yield Model for Submicron Domain. DFT 1997: 2-10 - Witold A. Pleskacz, Wojciech Maly, Hans T. Heineken:
Detection of Yield Trends. DFT 1997: 62-68 - John R. Samson Jr., Wilfrido Alejandro Moreno, Fernando J. Falquez:
Validating fault tolerant designs using laser fault injection (LFI). DFT 1997: 175-185 - Stephen J. Spinks, Chris D. Chalk, Ian M. Bell, Mark Zwolinski:
Generation and Verification of Tests for Analogue Circuits Subject to Process Parameter Deviations. DFT 1997: 100-109
