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2020 – today
- 2024
[c58]Yueqi Wang
, Bingyao Li, Aamer Jaleel, Jun Yang, Xulong Tang:
GRIT: Enhancing Multi-GPU Performance with Fine-Grained Dynamic Page Placement. HPCA 2024: 1080-1094- [c57]Aamer Jaleel, Gururaj Saileshwar, Stephen W. Keckler, Moinuddin K. Qureshi:
PrIDE: Achieving Secure Rowhammer Mitigation with Low-Cost In-DRAM Trackers. ISCA 2024: 1157-1172 - [c56]Bingyao Li, Yueqi Wang, Tianyu Wang, Lieven Eeckhout, Jun Yang, Aamer Jaleel, Xulong Tang:
STAR: Sub-Entry Sharing-Aware TLB for Multi-Instance GPU. MICRO 2024: 309-323 - [c55]Moinuddin Qureshi, Salman Qazi, Aamer Jaleel:
MINT: Securely Mitigating Rowhammer with a Minimalist in-DRAM Tracker. MICRO 2024: 899-914 - [c54]Anish Saxena, Aamer Jaleel, Moinuddin Qureshi:
ImPress: Securing DRAM Against Data-Disturbance Errors via Implicit Row-Press Mitigation. MICRO 2024: 935-948 - [i6]Aamer Jaleel, Stephen W. Keckler, Gururaj Saileshwar:
Probabilistic Tracker Management Policies for Low-Cost and Scalable Rowhammer Mitigation. CoRR abs/2404.16256 (2024) - [i5]Bingyao Li, Yueqi Wang, Tianyu Wang, Lieven Eeckhout, Jun Yang, Aamer Jaleel, Xulong Tang:
Improving Multi-Instance GPU Efficiency via Sub-Entry Sharing TLB Design. CoRR abs/2404.18361 (2024) - [i4]Moinuddin K. Qureshi, Anish Saxena, Aamer Jaleel:
ImPress: Securing DRAM Against Data-Disturbance Errors via Implicit Row-Press Mitigation. CoRR abs/2407.16006 (2024) - [i3]Moinuddin Qureshi, Salman Qazi, Aamer Jaleel:
MINT: Securely Mitigating Rowhammer with a Minimalist In-DRAM Tracker. CoRR abs/2407.16038 (2024) - 2023
- [j16]Mohamed Tarek Ibn Ziad, Sana Damani, Aamer Jaleel, Stephen W. Keckler, Mark Stephenson:
cuCatch: A Debugging Tool for Efficiently Catching Memory Safety Violations in CUDA Applications. Proc. ACM Program. Lang. 7(PLDI): 124-147 (2023) - [j15]Michael Pellauer, Jason Clemons, Vignesh Balaji, Neal Clayton Crago, Aamer Jaleel, Donghyuk Lee, Mike O'Connor, Anghsuman Parashar, Sean Treichler, Po-An Tsai, Stephen W. Keckler, Joel S. Emer:
Symphony: Orchestrating Sparse and Dense Tensors with Hierarchical Heterogeneous Processing. ACM Trans. Comput. Syst. 41: 4:1-4:30 (2023) - [c53]Toluwanimi O. Odemuyiwa, Hadi Asghari Moghaddam, Michael Pellauer, Kartik Hegde, Po-An Tsai, Neal Clayton Crago, Aamer Jaleel, John D. Owens, Edgar Solomonik, Joel S. Emer, Christopher W. Fletcher:
Accelerating Sparse Data Orchestration via Dynamic Reflexive Tiling. ASPLOS (3) 2023: 18-32 - [c52]Toluwanimi O. Odemuyiwa, Hadi Asghari Moghaddam, Michael Pellauer, Kartik Hegde, Po-An Tsai, Neal Clayton Crago, Aamer Jaleel, John D. Owens, Edgar Solomonik, Joel S. Emer, Christopher W. Fletcher:
Accelerating Sparse Data Orchestration via Dynamic Reflexive Tiling (Extended Abstract). HOPC@SPAA 2023: 15-16 - [c51]Michael B. Sullivan, Mohamed Tarek Ibn Ziad, Aamer Jaleel, Stephen W. Keckler:
Implicit Memory Tagging: No-Overhead Memory Safety Using Alias-Free Tagged ECC. ISCA 2023: 67:1-67:13 - [c50]Vignesh Balaji, Neal Clayton Crago, Aamer Jaleel, Stephen W. Keckler:
Community-based Matrix Reordering for Sparse Linear Algebra Optimization. ISPASS 2023: 214-223 - [c49]Bingyao Li, Yanan Guo, Yueqi Wang, Aamer Jaleel, Jun Yang, Xulong Tang:
IDYLL: Enhancing Page Translation in Multi-GPUs via Light Weight PTE Invalidations. MICRO 2023: 1163-1177 - [c48]Yaosheng Fu, Evgeny Bolotin, Aamer Jaleel, Gal Dalal, Shie Mannor, Jacob Subag, Noam Korem, Michael Behar, David W. Nellans:
AutoScratch: ML-Optimized Cache Management for Inference-Oriented GPUs. MLSys 2023 - 2021
- [c47]Vignesh Balaji, Neal Clayton Crago, Aamer Jaleel, Brandon Lucia:
P-OPT: Practical Optimal Cache Replacement for Graph Analytics. HPCA 2021: 668-681 - 2020
- [c46]Xiaowei Ren, Daniel Lustig, Evgeny Bolotin, Aamer Jaleel, Oreste Villa, David W. Nellans:
HMG: Extending Cache Coherence Protocols Across Modern Hierarchical Multi-GPU Systems. HPCA 2020: 582-595
2010 – 2019
- 2019
- [j14]Aamer Jaleel, Eiman Ebrahimi, Sam Duncan:
DUCATI: High-performance Address Translation by Extending TLB Reach of GPU-accelerated Systems. ACM Trans. Archit. Code Optim. 16(1): 6:1-6:24 (2019) - [c45]Xia Zhao, Almutaz Adileh, Zhibin Yu, Zhiying Wang, Aamer Jaleel, Lieven Eeckhout:
Adaptive memory-side last-level GPU caching. ISCA 2019: 411-423 - [c44]Kartik Hegde, Hadi Asghari Moghaddam, Michael Pellauer, Neal Clayton Crago, Aamer Jaleel, Edgar Solomonik, Joel S. Emer, Christopher W. Fletcher:
ExTensor: An Accelerator for Sparse Tensor Algebra. MICRO 2019: 319-333 - 2018
- [c43]Vinson Young, Chia-Chen Chou, Aamer Jaleel, Moinuddin K. Qureshi:
ACCORD: Enabling Associativity for Gigascale DRAM Caches by Coordinating Way-Install and Way-Prediction. ISCA 2018: 328-339 - [c42]Vinson Young, Aamer Jaleel, Evgeny Bolotin, Eiman Ebrahimi, David W. Nellans, Oreste Villa:
Combining HW/SW Mechanisms to Improve NUMA Performance of Multi-GPU Systems. MICRO 2018: 339-351 - 2017
- [j13]Almutaz Adileh, Stijn Eyerman, Aamer Jaleel, Lieven Eeckhout:
Mind The Power Holes: Sifting Operating Points in Power-Limited Heterogeneous Multicores. IEEE Comput. Archit. Lett. 16(1): 56-59 (2017) - [j12]Aamer Jaleel, Moinuddin K. Qureshi:
Top Picks from the 2016 Computer Architecture Conferences. IEEE Micro 37(3): 6-11 (2017) - [c41]Mwaffaq Otoom, Aamer Jaleel, Pedro Trancoso:
Using Personality Metrics to Improve Cache Interference Management in Multicore Processors. Conf. Computing Frontiers 2017: 251-254 - [c40]Mehmet Kayaalp, Khaled N. Khasawneh, Hodjat Asghari Esfeden, Jesse Elwell, Nael B. Abu-Ghazaleh, Dmitry V. Ponomarev, Aamer Jaleel:
RIC: Relaxed Inclusion Caches for Mitigating LLC Side-Channel Attacks. DAC 2017: 7:1-7:6 - [c39]Akhil Arunkumar, Evgeny Bolotin, Benjamin Y. Cho, Ugljesa Milic, Eiman Ebrahimi, Oreste Villa, Aamer Jaleel, Carole-Jean Wu, David W. Nellans:
MCM-GPU: Multi-Chip-Module GPUs for Continued Performance Scalability. ISCA 2017: 320-332 - [c38]Chia-Chen Chou, Aamer Jaleel, Moinuddin K. Qureshi:
BATMAN: techniques for maximizing system bandwidth of memory systems with stacked-DRAM. MEMSYS 2017: 268-280 - [c37]Ugljesa Milic, Oreste Villa, Evgeny Bolotin, Akhil Arunkumar, Eiman Ebrahimi, Aamer Jaleel, Alex Ramírez, David W. Nellans:
Beyond the socket: NUMA-aware GPUs. MICRO 2017: 123-135 - 2016
- [j11]Almutaz Adileh, Stijn Eyerman, Aamer Jaleel, Lieven Eeckhout:
Maximizing Heterogeneous Processor Performance Under Power Constraints. ACM Trans. Archit. Code Optim. 13(3): 29:1-29:23 (2016) - [c36]Mehmet Kayaalp, Nael B. Abu-Ghazaleh, Dmitry V. Ponomarev, Aamer Jaleel:
A high-resolution side-channel attack on last-level cache. DAC 2016: 72:1-72:6 - [c35]Hsiang-Yun Cheng, Jishen Zhao, Jack Sampson, Mary Jane Irwin, Aamer Jaleel, Yu Lu, Yuan Xie:
LAP: Loop-Block Aware Inclusion Properties for Energy-Efficient Asymmetric Last Level Caches. ISCA 2016: 103-114 - [c34]Mohsen Ghasempour, Aamer Jaleel, Jim D. Garside, Mikel Luján:
HAPPY: Hybrid Address-based Page Policy in DRAMs. MEMSYS 2016: 311-321 - [c33]Mohsen Ghasempour, Aamer Jaleel, Jim D. Garside, Mikel Luján:
DReAM: Dynamic Re-arrangement of Address Mapping to Improve the Performance of DRAMs. MEMSYS 2016: 362-373 - [c32]Chia-Chen Chou, Aamer Jaleel, Moinuddin K. Qureshi:
CANDY: Enabling coherent DRAM caches for multi-node systems. MICRO 2016: 35:1-35:13 - [c31]Joshua San Miguel, Jorge Albericio, Natalie D. Enright Jerger, Aamer Jaleel:
The Bunker Cache for spatio-value approximation. MICRO 2016: 43:1-43:12 - 2015
- [j10]Muhammet Mustafa Ozdal, Aamer Jaleel, Paolo Narváez, Steven M. Burns, Ganapati Srinivasa:
Wavelet-Based Trace Alignment Algorithms for Heterogeneous Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(3): 381-394 (2015) - [j9]Michael Pellauer, Angshuman Parashar, Michael Adler, Bushra Ahsan, Randy L. Allmon, Neal Clayton Crago, Kermin Fleming, Mohit Gambhir, Aamer Jaleel, Tushar Krishna, Daniel Lustig, Stephen Maresh, Vladimir Pavlov, Rachid Rayess, Antonia Zhai, Joel S. Emer:
Efficient Control and Communication Paradigms for Coarse-Grained Spatial Architectures. ACM Trans. Comput. Syst. 33(3): 10:1-10:32 (2015) - [c30]Aamer Jaleel, Joseph Nuzman, Adrian Moga, Simon C. Steely Jr., Joel S. Emer:
High performing cache hierarchies for server workloads: Relaxing inclusion to capture the latency benefits of exclusive caches. HPCA 2015: 343-353 - [c29]Chia-Chen Chou, Aamer Jaleel, Moinuddin K. Qureshi:
BEAR: techniques for mitigating bandwidth bloat in gigascale DRAM caches. ISCA 2015: 198-210 - [i2]Mohsen Ghasempour, Jim D. Garside, Aamer Jaleel, Mikel Luján:
DReAM: Dynamic Re-arrangement of Address Mapping to Improve the Performance of DRAMs. CoRR abs/1509.03721 (2015) - [i1]Mohsen Ghasempour, Aamer Jaleel, Jim D. Garside, Mikel Luján:
HAPPY: Hybrid Address-based Page Policy in DRAMs. CoRR abs/1509.03740 (2015) - 2014
- [j8]Angshuman Parashar, Michael Pellauer, Michael Adler, Bushra Ahsan, Neal Clayton Crago, Daniel Lustig, Vladimir Pavlov, Antonia Zhai, Mohit Gambhir, Aamer Jaleel, Randy L. Allmon, Rachid Rayess, Stephen Maresh, Joel S. Emer:
Efficient Spatial Processing Element Control via Triggered Instructions. IEEE Micro 34(3): 120-137 (2014) - [c28]Seth H. Pugsley, Zeshan Chishti, Chris Wilkerson, Peng-fei Chuang, Robert L. Scott, Aamer Jaleel, Shih-Lien Lu, Kingsum Chow, Rajeev Balasubramonian:
Sandbox Prefetching: Safe run-time evaluation of aggressive prefetchers. HPCA 2014: 626-637 - [c27]Wim Heirman, Trevor E. Carlson, Kenzo Van Craeynest, Ibrahim Hur, Aamer Jaleel, Lieven Eeckhout:
Undersubscribed threading on clustered cache architectures. HPCA 2014: 678-689 - [c26]Wim Heirman, Trevor E. Carlson, Kenzo Van Craeynest, Ibrahim Hur, Aamer Jaleel, Lieven Eeckhout:
Automatic SMT threading for OpenMP applications on the Intel Xeon Phi co-processor. ROSS@ICS 2014: 7:1-7:7 - [c25]Chia-Chen Chou, Aamer Jaleel, Moinuddin K. Qureshi:
CAMEO: A Two-Level Memory Organization with Capacity of Main Memory and Flexibility of Hardware-Managed Cache. MICRO 2014: 1-12 - 2013
- [j7]Samantika Subramaniam, Simon C. Steely Jr., William Hasenplaugh, Aamer Jaleel, Carl J. Beckmann, Tryggve Fossum, Joel S. Emer:
Using in-flight chains to build a scalable cache coherence protocol. ACM Trans. Archit. Code Optim. 10(4): 28:1-28:24 (2013) - [c24]Kenzo Van Craeynest, Shoaib Akram, Wim Heirman, Aamer Jaleel, Lieven Eeckhout:
Fairness-aware scheduling on single-ISA heterogeneous multi-cores. PACT 2013: 177-187 - [c23]Muhammet Mustafa Ozdal, Aamer Jaleel, Paolo Narváez, Steven M. Burns, Ganapati Srinivasa:
Trace alignment algorithms for offline workload analysis of heterogeneous architectures. ICCAD 2013: 654-661 - [c22]Angshuman Parashar, Michael Pellauer, Michael Adler, Bushra Ahsan, Neal Clayton Crago, Daniel Lustig, Vladimir Pavlov, Antonia Zhai, Mohit Gambhir, Aamer Jaleel, Randy L. Allmon, Rachid Rayess, Stephen Maresh, Joel S. Emer:
Triggered instructions: a control paradigm for spatially-programmed architectures. ISCA 2013: 142-153 - 2012
- [j6]Leonid Domnitser, Aamer Jaleel, Jason Loew, Nael B. Abu-Ghazaleh, Dmitry Ponomarev:
Non-monopolizable caches: Low-complexity mitigation of cache side channel attacks. ACM Trans. Archit. Code Optim. 8(4): 35:1-35:21 (2012) - [j5]William Hasenplaugh, Pritpal S. Ahuja, Aamer Jaleel, Simon C. Steely Jr., Joel S. Emer:
The gradient-based cache partitioning algorithm. ACM Trans. Archit. Code Optim. 8(4): 44:1-44:21 (2012) - [c21]Aamer Jaleel, Hashem Hashemi Najaf-abadi, Samantika Subramaniam, Simon C. Steely Jr., Joel S. Emer:
CRUISE: cache replacement and utility-aware scheduling. ASPLOS 2012: 249-260 - [c20]Kenzo Van Craeynest, Aamer Jaleel, Lieven Eeckhout, Paolo Narváez, Joel S. Emer:
Scheduling heterogeneous multi-cores through performance impact estimation (PIE). ISCA 2012: 213-224 - [c19]Binh Pham, Viswanathan Vaidyanathan, Aamer Jaleel, Abhishek Bhattacharjee:
CoLT: Coalesced Large-Reach TLBs. MICRO 2012: 258-269 - 2011
- [c18]Carole-Jean Wu, Aamer Jaleel, William Hasenplaugh, Margaret Martonosi, Simon C. Steely Jr., Joel S. Emer:
SHiP: signature-based hit predictor for high performance caching. MICRO 2011: 430-441 - [c17]Carole-Jean Wu, Aamer Jaleel, Margaret Martonosi, Simon C. Steely Jr., Joel S. Emer:
PACMan: prefetch-aware cache management for high performance caching. MICRO 2011: 442-453 - 2010
- [j4]Moshe Bach, Mark Charney, Robert Cohn, Elena Demikhovsky, Tevi Devor, Kim M. Hazelwood, Aamer Jaleel, Chi-Keung Luk, Gail Lyons, Harish Patil, Ady Tal:
Analyzing Parallel Programs with Pin. Computer 43(3): 34-41 (2010) - [c16]Arijit Biswas, Charles Recchia, Shubhendu S. Mukherjee, Vinod Ambrose, Leo Chan, Aamer Jaleel, Athanasios E. Papathanasiou, Mike Plaster, Norbert Seifert:
Explaining cache SER anomaly using DUE AVF measurement. HPCA 2010: 1-12 - [c15]Aamer Jaleel, Kevin B. Theobald, Simon C. Steely Jr., Joel S. Emer:
High performance cache replacement using re-reference interval prediction (RRIP). ISCA 2010: 60-71 - [c14]Aamer Jaleel, Eric Borch, Malini Bhandaru, Simon C. Steely Jr., Joel S. Emer:
Achieving Non-Inclusive Cache Performance with Inclusive Caches: Temporal Locality Aware (TLA) Cache Management Policies. MICRO 2010: 151-162
2000 – 2009
- 2009
- [c13]Jaideep Moses, Konstantinos Aisopos, Aamer Jaleel, Ravi R. Iyer, Ramesh Illikkal, Donald Newell, Srihari Makineni:
CMPSched$im: Evaluating OS/CMP interaction on shared cache management. ISPASS 2009: 113-122 - [c12]Junmin Lin, Yu Chen, Wenlong Li, Aamer Jaleel, Zhizhong Tang:
Understanding the Memory Behavior of Emerging Multi-core Workloads. ISPDC 2009: 153-160 - 2008
- [j3]Moinuddin K. Qureshi, Aamer Jaleel, Yale N. Patt, Simon C. Steely Jr., Joel S. Emer:
Set-Dueling-Controlled Adaptive Insertion for High-Performance Caching. IEEE Micro 28(1): 91-98 (2008) - [c11]Aamer Jaleel, William Hasenplaugh, Moinuddin K. Qureshi, Julien Sebot, Simon C. Steely Jr., Joel S. Emer:
Adaptive insertion policies for managing shared caches. PACT 2008: 208-219 - [c10]Yu Chen, Wenlong Li, Junmin Lin, Aamer Jaleel, Zhizhong Tang:
Data Sharing Analysis of Emerging Parallel Media Mining Workloads. HiPC 2008: 87-96 - 2007
- [c9]Brinda Ganesh, Aamer Jaleel, David Wang, Bruce L. Jacob:
Fully-Buffered DIMM Memory Architectures: Understanding Mechanisms, Overheads and Scaling. HPCA 2007: 109-120 - [c8]Moinuddin K. Qureshi, Aamer Jaleel, Yale N. Patt, Simon C. Steely Jr., Joel S. Emer:
Adaptive insertion policies for high performance caching. ISCA 2007: 381-391 - [c7]Wenlong Li, Eric Q. Li, Aamer Jaleel, Jiulong Shan, Yurong Chen, Qigang Wang, Ravi R. Iyer, Ramesh Illikkal, Yimin Zhang, Dong Liu, Michael Liao, Wei Wei, Jinhua Du:
Understanding the Memory Performance of Data-Mining Workloads on Small, Medium, and Large-Scale CMPs Using Hardware-Software Co-simulation. ISPASS 2007: 35-43 - [c6]Erez Perelman, Jeremy Lau, Harish Patil, Aamer Jaleel, Greg Hamerly, Brad Calder:
Cross Binary Simulation Points. ISPASS 2007: 179-189 - 2006
- [j2]Aamer Jaleel, Bruce L. Jacob:
In-Line Interrupt Handling and Lock-Up Free Translation Lookaside Buffers (TLBs). IEEE Trans. Computers 55(5): 559-574 (2006) - [c5]Aamer Jaleel, Matthew Mattina, Bruce L. Jacob:
Last level cache (LLC) performance of data mining workloads on a CMP - a case study of parallel bioinformatics workloads. HPCA 2006: 88-98 - 2005
- [j1]David Wang, Brinda Ganesh, Nuengwong Tuaycharoen, Kathleen Baynes, Aamer Jaleel, Bruce L. Jacob:
DRAMsim: a memory system simulator. SIGARCH Comput. Archit. News 33(4): 100-107 (2005) - [c4]Aamer Jaleel, Bruce L. Jacob:
Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory Instructions. HPCA 2005: 191-200 - [c3]Kursad Albayraktaroglu, Aamer Jaleel, Xue Wu, Manoj Franklin, Bruce L. Jacob, Chau-Wen Tseng, Donald Yeung:
BioBench: A Benchmark Suite of Bioinformatics Applications. ISPASS 2005: 2-9 - 2001
- [c2]Aamer Jaleel, Bruce L. Jacob:
Improving the Precise Interrupt Mechanism of Software-Managed TLB Miss Handlers. HiPC 2001: 282-293 - [c1]Aamer Jaleel, Bruce L. Jacob:
In-Line Interrupt Handling for Software-Managed TLBs. ICCD 2001: 62-67
Coauthor Index
Moinuddin K. Qureshi
aka: Moinuddin Qureshi
aka: Moinuddin Qureshi
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