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2010 – 2019
- 2018
[c9]Vinson Young, Chia-Chen Chou, Aamer Jaleel, Moinuddin K. Qureshi:
ACCORD: Enabling Associativity for Gigascale DRAM Caches by Coordinating Way-Install and Way-Prediction. ISCA 2018: 328-339- 2017
- [c8]Chia-Chen Chou, Aamer Jaleel, Moinuddin K. Qureshi:
BATMAN: techniques for maximizing system bandwidth of memory systems with stacked-DRAM. MEMSYS 2017: 268-280 - 2016
- [c7]Chia-Chen Chou, Aamer Jaleel, Moinuddin K. Qureshi:
CANDY: Enabling coherent DRAM caches for multi-node systems. MICRO 2016: 35:1-35:13 - 2015
- [c6]Chia-Chen Chou, Prashant J. Nair, Moinuddin K. Qureshi:
Reducing Refresh Power in Mobile Devices with Morphable ECC. DSN 2015: 355-366 - [c5]Prashant J. Nair, Chia-Chen Chou, Bipin Rajendran
, Moinuddin K. Qureshi:
Reducing read latency of phase change memory via early read and Turbo Read. HPCA 2015: 309-319 - [c4]Chia-Chen Chou, Aamer Jaleel, Moinuddin K. Qureshi:
BEAR: techniques for mitigating bandwidth bloat in gigascale DRAM caches. ISCA 2015: 198-210 - 2014
- [j1]Prashant J. Nair, Chia-Chen Chou, Moinuddin K. Qureshi:
Refresh pausing in DRAM memory systems. ACM Trans. Archit. Code Optim. 11(1): 10:1-10:26 (2014) - [c3]Chia-Chen Chou, Aamer Jaleel, Moinuddin K. Qureshi:
CAMEO: A Two-Level Memory Organization with Capacity of Main Memory and Flexibility of Hardware-Managed Cache. MICRO 2014: 1-12 - 2013
- [c2]Prashant J. Nair, Chia-Chen Chou, Moinuddin K. Qureshi:
A case for Refresh Pausing in DRAM memory systems. HPCA 2013: 627-638 - 2010
- [c1]Yu-Hui Chen, Chia-Chen Chou, Hung-yi Lee, Lin-Shan Lee:
An initial attempt to improve spoken term detection by learning optimal weights for different indexing features. ICASSP 2010: 5278-5281
Coauthor Index
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