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Journal Articles
- 2000
[j8]Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen:
ALTO: an iterative area/performance tradeoff algorithm for LUT-based FPGA technology mapping. IEEE Trans. Very Large Scale Integr. Syst. 8(4): 392-400 (2000)- 1999
- [j7]Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou:
A structure-oriented power modeling technique for macrocells. IEEE Trans. Very Large Scale Integr. Syst. 7(3): 380-391 (1999) - 1998
- [j6]Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen, Hsien-Ho Chuang:
On circuit clustering for area/delay tradeoff under capacity and pin constraints. IEEE Trans. Very Large Scale Integr. Syst. 6(4): 634-642 (1998) - 1993
- [j5]Wen-Zen Shen, Gwo-Haur Hwang, Wen-Jun Hsu, Yun-Jung Jan:
Design of Pseudoexhaustive Testable PLA with Low Overhead. IEEE Trans. Computers 42(7): 887-891 (1993) - [j4]Gwo-Haur Hwang, Wen-Zen Shen:
Restructuring and logic minimization for testable PLA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(4): 488-496 (1993) - 1992
- [j3]Chung Len Lee, Ching Ping Wu, Wen-Zen Shen, Tyh-Song Hwang, Shueng Dar Hwang:
MT-SIM a mixed-level transition fault simulator based on parallel patterns. J. Electron. Test. 3(1): 67-78 (1992) - 1991
- [j2]Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen:
Checkpoints in irredundant two-level combinational circuits. J. Electron. Test. 2(4): 395-397 (1991) - [j1]Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen:
Single-fault fault-collapsing analysis in sequential logic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(12): 1559-1568 (1991)
Conference and Workshop Papers
- 2001
- [c17]Chih-Yang Hsu, Chaur-Wen Wei, Wen-Zen Shen:
A pattern compaction technique for power estimation based on power sensitivity information. ISCAS (5) 2001: 467-470 - [c16]Heng-Liang Huang, Yeong-Ren Chen, Jing-Yang Jou, Wen-Zen Shen:
Grouped input power sensitive transition an input sequence compaction technique for power estimation. ISCAS (5) 2001: 471-474 - 2000
- [c15]Heng-Liang Huang, Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou:
A new method for constructing IP level power model based on power sensitivity. ASP-DAC 2000: 135-140 - 1997
- [c14]Wen-Zen Shen, Jiing-Yuan Lin, Jyh-Ming Lu:
CB-Power: a hierarchical cell-based power characterization and estimation environment for static CMOS circuits. ASP-DAC 1997: 189-194 - [c13]Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou:
A power modeling and characterization method for macrocells using structure information. ICCAD 1997: 502-506 - 1996
- [c12]Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen:
An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping. ICCAD 1996: 13-17 - [c11]Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou:
A power modeling and characterization method for the CMOS standard cell library. ICCAD 1996: 400-404 - 1995
- [c10]Wen-Zen Shen, Jiing-Yuan Lin, Fong-Wen Wang:
Transistor reordering rules for power reduction in CMOS gates. ASP-DAC 1995 - [c9]Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen, Beyin Chen:
Fanout fault analysis for digital logic circuits. Asian Test Symposium 1995: 33-39 - [c8]Wen-Zen Shen, Juinn-Dar Huang, Shih-Min Chao:
Lambda Set Selection in Roth-Karp Decomposition for LUT-Based FPGA Technology Mapping. DAC 1995: 65-69 - [c7]Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen:
Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture. ICCAD 1995: 359-363 - 1994
- [c6]Jiing-Yuan Lin, Tai-Chien Liu, Wen-Zen Shen:
A cell-based power estimation in CMOS combinational circuits. ICCAD 1994: 304-309 - [c5]Wen-Zen Shen, Yi-Hsin Tao, Lan-Rong Dung:
On the Reduction of Recorder Buffer Size for Discrete Fourier Transform Processor Design. ISCAS 1994: 171-174 - 1992
- [c4]Wen-Jun Hsu, Wen-Zen Shen:
Coalgebraic Division for Multilevel Logic Synthesis. DAC 1992: 438-442 - [c3]Ching Ping Wu, Chung Len Lee, Wen-Zen Shen:
SEESIM - a fast synchronous sequential circuit fault simulator with single event equivalence. EURO-DAC 1992: 446-449 - 1990
- [c2]Tyh-Song Hwang, Chung Len Lee, Wen-Zen Shen, Ching Ping Wu:
A Parallel Pattern Mixed-Level Fault Simulator. DAC 1990: 716-719 - [c1]Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen:
Single-fault fault collapsing analysis in sequential logic circuits. ITC 1990: 809-814
Coauthor Index
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