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Journal Articles
- 2011
[j4]Osamu Nishii, Yoichi Yuyama, Masayuki Ito, Yoshikazu Kiyoshige, Yusuke Nitta, Makoto Ishikawa, Tetsuya Yamada, Junichi Miyakoshi, Yasutaka Wada
, Keiji Kimura, Hironori Kasahara, Hideo Maejima:
A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core. IEICE Trans. Electron. 94-C(4): 663-669 (2011)- 2008
- [j3]Hiroaki Shikano, Masaki Ito, Masafumi Onouchi, Takashi Todaka, Takanobu Tsunoda, Tomoyuki Kodama, Kunio Uchiyama, Toshihiko Odaka, Tatsuya Kamei, Ei Nagahama, Manabu Kusaoke, Yusuke Nitta, Yasutaka Wada, Keiji Kimura, Hironori Kasahara:
Heterogeneous Multi-Core Architecture That Enables 54x AAC-LC Stereo Encoding. IEEE J. Solid State Circuits 43(4): 902-910 (2008) - 2006
- [j2]Tetsuya Yamada, Masahide Abe, Yusuke Nitta, Kenji Ogura, Manabu Kusaoke, Makoto Ishikawa, Motokazu Ozawa, Kiwamu Takada, Fumio Arakawa, Osamu Nishii, Toshihiro Hattori:
Reducing Consuming Clock Power Optimization of a 90 nm Embedded Processor Core. IEICE Trans. Electron. 89-C(3): 287-294 (2006) - 1993
- [j1]Masato Soga, Jun'ichi Toyoda, Yusuke Nitta, Takeshi Imanaka, Masuzo Yanagida:
Generation of a hierarchical representation for graphic patterns based on grouping. Syst. Comput. Jpn. 24(2): 70-87 (1993)
Conference and Workshop Papers
- 2010
- [c4]Yoichi Yuyama, Masayuki Ito, Yoshikazu Kiyoshige, Yusuke Nitta, Shigezumi Matsui, Osamu Nishii, Atsushi Hasegawa, Makoto Ishikawa, Tetsuya Yamada, Junichi Miyakoshi, Koichi Terada, Tohru Nojiri, Masashi Satoh, Hiroyuki Mizuno, Kunio Uchiyama, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, Hideo Maejima:
A 45nm 37.3GOPS/W heterogeneous multi-core SoC. ISSCC 2010: 100-101 - 2007
- [c3]Makoto Saen, Kenichi Osada, Satoshi Misaka, Tetsuya Yamada, Yoshitaka Tsujimoto, Yuki Kondo, Tatsuya Kamei, Yutaka Yoshida, Ei Nagahama, Yusuke Nitta, Takayasu Ito, Tadashi Kameyama, Naohiko Irie:
Embedded SoC Resource Manager to Control Temperature and Data Bandwidth. ISSCC 2007: 296-604 - 2005
- [c2]Tetsuya Yamada, Masahide Abe, Yusuke Nitta, Kenji Ogura, Manabu Kusaoke, Makoto Ishikawa, Motokazu Ozawa, Kiwamu Takada, Fumio Arakawa, Osamu Nishii, Toshihiro Hattori:
Low-Power Design of 90-nm SuperH Processor Core. ICCD 2005: 258-266 - 1998
- [c1]Toshihiro Hattori, Yusuke Nitta, Mitsuho Seki, Susumu Narita, Kunio Uchiyama, Tsuyoshi Takahashi, Ryuichi Satomura:
Design Methodology of a 200MHz Superscalar Microprocessor: SH-4. DAC 1998: 246-249
Coauthor Index
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