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ORCIDAndrzej Hlawiczka
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2010 – 2019
- 2010
[c18]Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka:
How to reduce size of a signature-based diagnostic dictionary used for testing of connections. DDECS 2010: 201-204- [c17]Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka:
Reduced-size signature-based diagnostic dictionary for interconnection testing. PDeS 2010: 82-87
2000 – 2009
- 2009
- [c16]Tomasz Rudnicki
, Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka:
Effective BIST for crosstalk faults in interconnects. DDECS 2009: 164-169 - 2008
- [c15]Andrzej Hlawiczka, Krzysztof Gucwa, Tomasz Garbolino, Michal Kopec:
Interconnect Faults Identification and Localization Using Modified Ring LFSRs. DDECS 2008: 247-250 - 2007
- [c14]Tomasz Garbolino, Krzysztof Gucwa, Michal Kopec, Andrzej Hlawiczka:
Avoiding Crosstalk Influence on Interconnect Delay Fault Testing. DDECS 2007: 149-152 - [c13]Tomasz Rudnicki, Andrzej Hlawiczka:
Test Pattern Generator for Delay Faults. DDECS 2007: 255-258 - 2006
- [c12]Tomasz Garbolino, Michal Kopec, Krzysztof Gucwa, Andrzej Hlawiczka:
Detection, Localisation and Identification of Interconnection Faults Using MISR Compactor. DDECS 2006: 230-231 - [c11]Michal Kopec, Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka:
Test-per-Clock Detection, Localization and Identification of Interconnect Faults. ETS 2006: 233-238 - 2004
- [j5]Ondrej Novák, Zdenek Plíva, Jiri Nosek, Andrzej Hlawiczka, Tomasz Garbolino, Krzysztof Gucwa:
Test-Per-Clock Logic BIST with Semi-Deterministic Test Patterns and Zero-Aliasing Compactor. J. Electron. Test. 20(1): 109-122 (2004) - 2002
- [j4]Tomasz Garbolino, Andrzej Hlawiczka:
Efficient test pattern generators based on specific cellular automata structures. Microelectron. Reliab. 42(6): 975-983 (2002) - [c10]Andrzej Hlawiczka, Michal Kopec:
Dependable testing of compactor MISR: an imperceptible problem? ETW 2002: 31-36 - 2000
- [c9]Andrzej Hlawiczka, Michal Kopec:
Design and testing of fast and cost effective serial seeding TPGs based on one-dimensional linear hybrid cellular automata. Asian Test Symposium 2000: 380-385 - [c8]Tomasz Garbolino, Andrzej Hlawiczka, Adam Kristof:
Fast and low-area TPGs based on T-type flip-flops can be easily integrated to the scan path. ETW 2000: 161-166
1990 – 1999
- 1999
- [c7]Tomasz Garbolino, Andrzej Hlawiczka:
A New LFSR with D and T Flip-Flops as an Effective Test Pattern Generator for VLSI Circuits. EDCC 1999: 321-338 - 1997
- [c6]Dariusz Badura, Andrzej Hlawiczka:
Low Cost Bist for Edac Circuits. Asian Test Symposium 1997: 410-415 - [c5]Andrzej Hlawiczka, Michael Gössel, Egor S. Sogomonyan:
A linear code-preserving signature analyzer COPMISR. VTS 1997: 350-355 - 1996
- [e1]Andrzej Hlawiczka, João Gabriel Silva, Luca Simoncini:
Dependable Computing - EDCC-2, Second European Dependable Computing Conference, Taormina, Italy, October 2-4, 1996, Proceedings. Lecture Notes in Computer Science 1150, Springer 1996, ISBN 3-540-61772-8 [contents] - 1994
- [c4]Andrzej Hlawiczka, Jacek Binda:
Optimized Synthesis of Self-Testable Finite State Machines (FSM) Using BIST-PST Structures in Altera Structures. FPL 1994: 120-122 - 1992
- [j3]Andrzej Hlawiczka:
Parallel Signature Analyzers Using Hybrid Design of Their Linear Feedbacks. IEEE Trans. Computers 41(12): 1562-1571 (1992)
1980 – 1989
- 1989
- [c3]Andrzej Hlawiczka:
Signature Analysis Testing with Bottom-Top Exclusive Or Type MISR. Fehlertolerierende Rechensysteme 1989: 356-367 - 1987
- [c2]Andrzej Hlawiczka, Dariusz Badura:
Universal Test Controller Chip for Board Self Test. Fehlertolerierende Rechensysteme 1987: 165-175 - 1986
- [j2]Andrzej Hlawiczka:
Compression of Three-State Data Serial Streams by Means of a Parallel LFSR Signature Analyzer. IEEE Trans. Computers 35(8): 732-741 (1986) - 1984
- [c1]Andrzej Hlawiczka:
Compression of multiple-valued data serial streams by means of parallel LFSR signature analyzer. Fehlertolerierende Rechensysteme 1984: 404-416
1970 – 1979
- 1978
- [j1]Andrzej Hlawiczka:
Comments on "Procedures for Eliminating Static and Dynamic-Hazards in Test Generation". IEEE Trans. Computers 27(2): 191 (1978)
Coauthor Index
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