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ORCIDTomasz Garbolino
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2010 – 2019
- 2014
[c13]Tomasz Garbolino:
Designing of Test Pattern Generators for stimulation of crosstalk faults in bus-type connections. DDECS 2014: 270-273- 2011
- [c12]Gregor Papa
, Tomasz Garbolino:
Optimal on-line built-in self-test structure for system-reliability improvement. IEEE Congress on Evolutionary Computation 2011: 222-229 - 2010
- [j3]Tomasz Garbolino, Gregor Papa:
Genetic algorithm for test pattern generator design - Automatic evolution of circuits. Appl. Intell. 32(2): 193-204 (2010) - [c11]Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka:
How to reduce size of a signature-based diagnostic dictionary used for testing of connections. DDECS 2010: 201-204 - [c10]Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka:
Reduced-size signature-based diagnostic dictionary for interconnection testing. PDeS 2010: 82-87
2000 – 2009
- 2009
- [c9]Tomasz Rudnicki, Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka:
Effective BIST for crosstalk faults in interconnects. DDECS 2009: 164-169 - 2008
- [c8]Andrzej Hlawiczka, Krzysztof Gucwa, Tomasz Garbolino, Michal Kopec:
Interconnect Faults Identification and Localization Using Modified Ring LFSRs. DDECS 2008: 247-250 - [c7]Gregor Papa, Tomasz Garbolino, Franc Novak:
Deterministic Test Pattern Generator Design. EvoWorkshops 2008: 204-213 - [c6]Tomasz Garbolino, Gregor Papa:
Test Pattern Generator Design Optimization Based on Genetic Algorithm. IEA/AIE 2008: 580-589 - 2007
- [c5]Tomasz Garbolino, Krzysztof Gucwa, Michal Kopec, Andrzej Hlawiczka:
Avoiding Crosstalk Influence on Interconnect Delay Fault Testing. DDECS 2007: 149-152 - [e1]Patrick Girard, Andrzej Krasniewski, Elena Gramatová, Adam Pawlak, Tomasz Garbolino:
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), Kraków, Poland, April 11-13, 2007. IEEE Computer Society 2007, ISBN 1-4244-1161-0 [contents] - 2006
- [c4]Tomasz Garbolino, Michal Kopec, Krzysztof Gucwa, Andrzej Hlawiczka:
Detection, Localisation and Identification of Interconnection Faults Using MISR Compactor. DDECS 2006: 230-231 - [c3]Michal Kopec, Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka:
Test-per-Clock Detection, Localization and Identification of Interconnect Faults. ETS 2006: 233-238 - 2004
- [j2]Ondrej Novák, Zdenek Plíva, Jiri Nosek, Andrzej Hlawiczka, Tomasz Garbolino, Krzysztof Gucwa:
Test-Per-Clock Logic BIST with Semi-Deterministic Test Patterns and Zero-Aliasing Compactor. J. Electron. Test. 20(1): 109-122 (2004) - 2002
- [j1]Tomasz Garbolino, Andrzej Hlawiczka:
Efficient test pattern generators based on specific cellular automata structures. Microelectron. Reliab. 42(6): 975-983 (2002) - 2000
- [c2]Tomasz Garbolino, Andrzej Hlawiczka, Adam Kristof:
Fast and low-area TPGs based on T-type flip-flops can be easily integrated to the scan path. ETW 2000: 161-166
1990 – 1999
- 1999
- [c1]Tomasz Garbolino, Andrzej Hlawiczka:
A New LFSR with D and T Flip-Flops as an Effective Test Pattern Generator for VLSI Circuits. EDCC 1999: 321-338
Coauthor Index
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