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2020 – today
- 2021
[j6]Shinya Ito
, Yufei Si, Alan M. Litke, David A. Feldheim:
Nonlinear visuoauditory integration in the mouse superior colliculus. PLoS Comput. Biol. 17(11) (2021)
2010 – 2019
- 2017
- [c8]Taisuke Masuta, Shinya Ito, Daiki Kobauashi, Hideaki Ohtake:
Impact of generator failures on photovoltaic energy curtailment in power systems with large-scale integration of photovoltaic generation. ICIIS 2017: 1-6 - 2016
- [j5]Nicholas M. Timme, Shinya Ito, Maxym Myroshnychenko, Sunny Nigam, Masanori Shimono, Fang-Chin Yeh, Pawel Hottowy, Alan M. Litke, John M. Beggs:
High-Degree Neurons Feed Cortical Computations. PLoS Comput. Biol. 12(5) (2016) - 2011
- [j4]Koichi Takeda, Toshio Saito, Shinobu Asayama, Yoshiharu Aimoto, Hiroyuki Kobatake, Shinya Ito, Toshifumi Takahashi, Masahiro Nomura, Kiyoshi Takeuchi, Yoshihiro Hayashi:
Multi-Step Word-Line Control Technology in Hierarchical Cell Architecture for Scaled-Down High-Density SRAMs. IEEE J. Solid State Circuits 46(4): 806-814 (2011)
2000 – 2009
- 2007
- [c7]Hemant Joshi, Shinya Ito, Santhosh Kanala, Sangeetha Hebbar, Coskun Bayrak:
Concept set extraction with user session context. ACM Southeast Regional Conference 2007: 455-460 - [c6]Takae Sakai, Shinya Ito, Nobuyoshi Kaiki, Atsushi Sakai, Mamoru Okazaki, Masayuki Natsumi, Akira Saito, Kazumasa Kioi, Masato Koutani, Koutani Kagoshima, Shuichi Kawama, Hiroshi Kijima, Shinji Toyoyama, Nobutoshi Matsunaga, Mutsumi Hamaguchi, Hiroshi Kawamura, Kunihiko Iizuka:
A Digital TV Receiver RF and BB Chipset with Adaptive Bias-Current Control for Mobile Applications. ISSCC 2007: 212-597 - [c5]Shinya Ito, Kenji Yoshigoe:
Exponentially Aggressive Preservation of Nearly Depleted Nodes for Wireless Sensor Networks. ITNG 2007: 880-882 - [c4]Shinya Ito, Kenji Yoshigoe:
Consumed-energy-type-aware routing for wireless sensor networks. WTS 2007: 1-6 - 2006
- [j3]Shinya Ito, Hiroshi Tsubokawa:
A method of digital watermarking by using the frequency masking effect. Syst. Comput. Jpn. 37(11): 79-87 (2006) - 2004
- [c3]Shinya Ito, Shouhei Nomoto, Hiroshi Tomiyasu, Hiroaki Nishikawa:
The Microarchitecture of the CUE-v2 Processor: Enabling the Simultaneous Processing of Dataflow and Control-Flow Threads. PDPTA 2004: 525-531 - 2002
- [j2]Shinya Ito, Hiroaki Namba, Tsuyoshi Hirata, Koichi Ando, Shin Koyama, Nobuyuki Ikezawa, Tatsuya Suzuki, Takehiro Saitoh, Tadahiko Horiuchi:
Effect of mechanical stress induced by etch-stop nitride: impact on deep-submicron transistor performance. Microelectron. Reliab. 42(2): 201-209 (2002) - [c2]Shinya Ito, Ryosuke Kurebayashi, Hiroaki Nishikawa:
A Self-evolutionary Emulation Scheme for A Networking Oriented Data-driven Processor Architecture: CUE. PDPTA 2002: 1082-1088 - 2001
- [j1]Kenji Noda, Koichi Takeda, Koujirou Matsui, Shinya Ito, Sadaaki Masuoka, Hideaki Kawamoto, Nobuyuki Ikezawa, Yoshiharu Aimoto, Noritsugu Nakamura, Takahiro Iwasaki, Hideo Toyoshima, Tadahiko Horiuchi:
An ultrahigh-density high-speed loadless four-transistor SRAM macro with twisted bitline architecture and triple-well shield. IEEE J. Solid State Circuits 36(3): 510-515 (2001) - 2000
- [c1]Kenji Noda, Koujirou Matsui, Shinya Ito, Sadaaki Masuoka, Hiroyuki Kawamoto, Nobuyuki Ikezawa, Koichi Takeda, Yoshiharu Aimoto, Naoto Nakamura, Hideo Toyoshima, Takahiro Iwasaki, Tadahiko Horiuchi:
An ultra-high-density high-speed loadless four-transistor SRAM macro with a dual-layered twisted bit-line and a triple-well shield. CICC 2000: 283-286
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