"An ultrahigh-density high-speed loadless four-transistor SRAM macro with ..."

Kenji Noda et al. (2001)

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DOI: 10.1109/4.910490

access: closed

type: Journal Article

metadata version: 2022-04-04

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Kenji Noda, Koichi Takeda, Koujirou Matsui, Shinya Ito, Sadaaki Masuoka, Hideaki Kawamoto, Nobuyuki Ikezawa, Yoshiharu Aimoto, Noritsugu Nakamura, Takahiro Iwasaki, Hideo Toyoshima, Tadahiko Horiuchi:
An ultrahigh-density high-speed loadless four-transistor SRAM macro with twisted bitline architecture and triple-well shield. IEEE J. Solid State Circuits 36(3): 510-515 (2001)

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