"An ultra-high-density high-speed loadless four-transistor SRAM macro with ..."

Kenji Noda et al. (2000)

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DOI: 10.1109/CICC.2000.852667

access: closed

type: Conference or Workshop Paper

metadata version: 2022-10-10

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Kenji Noda, Koujirou Matsui, Shinya Ito, Sadaaki Masuoka, Hiroyuki Kawamoto, Nobuyuki Ikezawa, Koichi Takeda, Yoshiharu Aimoto, Naoto Nakamura, Hideo Toyoshima, Takahiro Iwasaki, Tadahiko Horiuchi:
An ultra-high-density high-speed loadless four-transistor SRAM macro with a dual-layered twisted bit-line and a triple-well shield. CICC 2000: 283-286

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