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Conference and Workshop Papers
- 2024
[c10]Steven Demuynck, Victor Vega-Gonzalez, C. Toledo de Carvalho Cavalcante, L. Petersen Barbosa Lima, K. Stiers, C. Sheng, A. Vandooren, M. Hosseini, X. Zhou, Hans Mertens, Thomas Chiarella, Jürgen Bömmels, Roger Loo, E. Rosseel, Clement Porret, Y. Shimura, A. Akula, G. Mannaert, S. Choudhury, V. Brissonneau, E. Dupuy, T. Sarkar, Nathali Franchina-Vergel, A. Peter, Nicolas Jourdan, J. P. Soulie, Kevin Vandersmissen, F. Sebaai, P. Puttarame Gowda, K. Lai, A. Mingardi, S. Sumar Sarkar, K. D'Have, B. T. Chan, A. Sepulveda Marquez, R. Langer, I. Gyo Koo, E. Altamirano Sanchez, Katia Devriendt, P. Rincon Delgadillo, F. Lazzarino, Jérôme Mitard, J. Geypen, E. Grieten, D. Batuk, Y.-F. Chen, F. Verbeek, F. Holsteyns, S. Subramanian, N. Horiguchi, S. Biesemans:
Monolithic Complementary Field Effect Transistors (CFET) Demonstrated using Middle Dielectric Isolation and Stacked Contacts. VLSI Technology and Circuits 2024: 1-2- [c9]P. Zhao, Liesbeth Witters, Anne Jourdain, Michele Stucchi, Nicolas Jourdan, J. W. Maes, H. Bana, C. Zhu, R. Chukka, F. Sebaai, Kevin Vandersmissen, N. Heylen, D. Montero, S. Wang, K. D'Have, F. Schleicher, J. De Vos, Gerald Beyer, A. Miller, Eric Beyne:
Backside Power Delivery with relaxed overlay for backside patterning using extreme wafer thinning and Molybdenum-filled slit nano Through Silicon Vias. VLSI Technology and Circuits 2024: 1-2 - 2023
- [c8]Hans Mertens, M. Hosseini, Thomas Chiarella, D. Zhou, S. Wang, G. Mannaert, E. Dupuy, D. Radisic, Z. Tao, Yusuke Oniki, Andriy Hikavyy, R. Rosseel, A. Mingardi, S. Choudhury, P. Puttarame Gowda, F. Sebaai, A. Peter, Kevin Vandersmissen, J. P. Soulie, An De Keersgieter, L. Petersen Barbosa Lima, C. Cavalcante, D. Batuk, G. T. Martinez, J. Geypen, F. Seidel, K. Paulussen, P. Favia, Jürgen Bömmels, Roger Loo
, P. Wong, A. Sepulveda Marquez, B. T. Chan, Jérôme Mitard, S. Subramanian, S. Demuynck, E. Dentoni Litta, N. Horiguchi, S. Samavedam, S. Biesemans:
Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning. VLSI Technology and Circuits 2023: 1-2 - [c7]Victor Vega-Gonzalez, D. Radisic, Bt Chan, S. Choudhury, S. Wang, A. Mingardi, Q. Toan Le, H. Decoster, Yusuke Oniki, P. Puttarame, Kevin Vandersmissen, J. P. Soulie, A. Peter, A. Sepulveda, D. Batuk, G. T. Martinez, Olivier Richard, Jürgen Bömmels, S. Biesemans, E. Dentoni Litta, Naoto Horiguchi, Seongho Park, Zsolt Tokei:
Integration of a Stacked Contact MOL for Monolithic CFET. VLSI Technology and Circuits 2023: 1-2 - 2022
- [c6]S. Subhechha, Nouredine Rassoul, Attilio Belmonte, Hubert Hody, Harold Dekkers, Michiel J. van Setten, Adrian Vaisman Chasin, Shamin H. Sharifi, K. Banerjee, H. Puliyalil, Shreya Kundu, M. Pak, D. Tsvetanova, Nina Bazzazian, Kevin Vandersmissen, D. Batuk, J. Geypen, J. Heijlen, Romain Delhougne, Gouri Sankar Kar:
Device engineering guidelines for performance boost in IGZO front gated TFTs based on defect control. ICICDT 2022: 88 - [c5]Anabela Veloso, Anne Jourdain, D. Radisic, Rongmei Chen, G. Arutchelvan, B. O'Sullivan, Hiroaki Arimura, Michele Stucchi, An De Keersgieter, M. Hosseini, T. Hopf, K. D'Have, S. Wang, E. Dupuy, G. Mannaert, Kevin Vandersmissen, S. Iacovo, P. Marien, S. Choudhury, F. Schleicher, F. Sebaai, Yusuke Oniki, X. Zhou, A. Gupta, Tom Schram, B. Briggs, C. Lorant, E. Rosseel, Andriy Hikavyy, Roger Loo, J. Geypen, D. Batuk, G. T. Martinez, J. P. Soulie, Katia Devriendt, B. T. Chan, S. Demuynck, Gaspard Hiblot, Geert Van der Plas, Julien Ryckaert, Gerald Beyer, E. Dentoni Litta, Eric Beyne, Naoto Horiguchi:
Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails. VLSI Technology and Circuits 2022: 284-285 - [c4]S. Subhechha, Nouredine Rassoul, Attilio Belmonte, Hubert Hody, Harold Dekkers, Michiel J. van Setten, Adrian Vaisman Chasin, Shamin H. Sharifi, S. Sutar, L. Magnarin, Umberto Celano, H. Puliyalil, Shreya Kundu, M. Pak, Lieve Teugels, D. Tsvetanova, Nina Bazzazian, Kevin Vandersmissen, C. Biasotto, D. Batuk, J. Geypen, J. Heijlen, Romain Delhougne, Gouri Sankar Kar:
Ultra-low Leakage IGZO-TFTs with Raised Source/Drain for Vt > 0 V and Ion > 30 µA/µm. VLSI Technology and Circuits 2022: 292-293 - [c3]A. Vandooren, N. Parihar, Jacopo Franco, Roger Loo, Hiroaki Arimura, R. Rodriguez, F. Sebaai, S. Iacovo, Kevin Vandersmissen, W. Li, G. Mannaert, D. Radisic, E. Rosseel, Andriy Hikavyy, Anne Jourdain, O. Mourey, G. Gaudin, Shay Reboh, L. Le Van-Jodin, Guillaume Besnard, C. Roda Neve, Bich-Yen Nguyen, Iuliana P. Radu, E. Dentoni Litta, N. Horiguchi:
Demonstration of 3D sequential FD-SOI on CMOS FinFET stacking featuring low temperature Si layer transfer and top tier device fabrication with tier interconnections. VLSI Technology and Circuits 2022: 330-331 - 2021
- [c2]Cheng Han Wu, Steven Brems, Didit Yudistira, Daire Cott, A. Milenin, Kevin Vandersmissen, A. Maestre, A. Centeno, Joris Van Campenhout, Cedric Huyghebaert, Marianna Pantouvaki:
Graphene electro-absorption modulators integrated at wafer-scale in a CMOS fab. VLSI Circuits 2021: 1-2 - 2014
- [c1]Fumihiro Inoue, Harold Philipsen, Marleen H. van der Veen, Kevin Vandersmissen, Stefaan Van Huylenbroeck, Herbert Struyf, Tetsu Tanaka:
Cu seeding using electroless deposition on Ru liner for high aspect ratio through-Si vias. 3DIC 2014: 1-4
Coauthor Index
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