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2020 – today
- 2023
[j2]Zeeshan Ali
, Pallavi Paliwal, Phani Raj, Deepak Anand, Debasattam Pal, Shalabh Gupta:
Stability Analysis for Fast Settling Switched Digital Phase-Locked Loops (DPLLs). IEEE Control. Syst. Lett. 7: 1393-1398 (2023)- 2022
- [c7]Zeeshan Ali, Pallavi Paliwal, Rupesh Lad, Dhanraj Bhukya, Shalabh Gupta:
A Fast Locking Ring Oscillator Based Fractional-N DPLL With an Assistance From a LUT-Based FSM. ISCAS 2022: 2745-2749 - 2020
- [j1]Pallavi Paliwal, Vivek Yadav, Zeeshan Ali, Shalabh Gupta:
A Fast Settling Fractional-N DPLL With Loop-Order Switching. IEEE Trans. Very Large Scale Integr. Syst. 28(3): 714-725 (2020)
2010 – 2019
- 2019
- [c6]Arun Goyal, Souvik Ghosh, Sandeep Goyal, Pallavi Paliwal, Shalabh Gupta:
A High-Resolution Digital Phase Interpolator Based CDR with a Half-Rate Hybrid Phase Detector. ISCAS 2019: 1-5 - 2018
- [i1]Pallavi Paliwal, Debasattam Pal, Shalabh Gupta:
Stability Analysis for Fast Settling Switched DPLL. CoRR abs/1806.01209 (2018) - 2016
- [c5]Harishankar Sahu, Pallavi Paliwal, Vivek Yadav, Shalabh Gupta:
A low-jitter digital-to-time converter with look-ahead multi-phase DDS. LASCAS 2016: 219-222 - [c4]Pallavi Paliwal, Jaydip Fadadu, Anil Chawda, Shalabh Gupta:
A Fast Settling 4.7-5 GHz Fractional-N Digital Phase Locked Loop. VLSID 2016: 553-554 - 2014
- [c3]Anil Chawda, Pallavi Paliwal, Priyank Laad, Shalabh Gupta:
High resolution digital-to-time converter for low jitter digital PLLs. ICECS 2014: 25-28 - 2013
- [c2]Pallavi Paliwal, Priyank Laad, Mohanrao Sattineni, Shalabh Gupta:
Tradeoffs between settling time and jitter in phase locked loops. MWSCAS 2013: 746-749 - 2012
- [c1]Angada B. Sachid, Pallavi Paliwal, S. Joshi, Maryam Shojaei Baghini, Dinesh Sharma, V. Ramgopal Rao:
Circuit Optimization at 22nm Technology Node. VLSI Design 2012: 322-327
Coauthor Index
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