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Anil Chawda

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2010 – 2019

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2016
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  dblp key:
  - conf/vlsid/PaliwalFCG16
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  persistent URL:
  - https://dblp.org/rec/conf/vlsid/PaliwalFCG16
Pallavi Paliwal, Jaydip Fadadu, Anil Chawda, Shalabh Gupta:
A Fast Settling 4.7-5 GHz Fractional-N Digital Phase Locked Loop. VLSID 2016: 553-554
2014
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Anil Chawda, Pallavi Paliwal, Priyank Laad, Shalabh Gupta:
High resolution digital-to-time converter for low jitter digital PLLs. ICECS 2014: 25-28

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