• case-insensitive prefix search: default
  e.g., sig matches "SIGIR" as well as "signal"
• exact word search: append dollar sign ($) to word
  e.g., graph$ matches "graph", but not "graphics"
• boolean and: separate words by space
  e.g., codd model
• boolean or: connect words by pipe symbol (|)
  e.g., graph|network

Update May 7, 2017: Please note that we had to disable the phrase search operator (.) and the boolean not operator (-) due to technical problems. For the time being, phrase search queries will yield regular prefix search result, and search terms preceded by a minus will be interpreted as regular (positive) search terms.

found 16 matches

• 1995
• 
  Sati Banerjee, Paul M. Chau, Ronald D. Fellman:
  Rapid prototyping methodology for multiprocessor implementation of digital signal processing systems. J. VLSI Signal Process. 11(1-2): 21-34 (1995)
• 
  Magdy A. Bayoumi:
  Introduction. J. VLSI Signal Process. 11(1-2): 5-6 (1995)
• 
  Dusan Caf, David J. Evans:
  A fast solution of banded circulant systems. J. VLSI Signal Process. 11(3): 263-271 (1995)
• 
  Giuseppe Caire, Javier Ventura-Traveset, J. Murphy, Sun-Yuan Kung:
  Parallel and pipelined VLSI implementation of a staged decoder for BCM signals. J. VLSI Signal Process. 11(3): 195-211 (1995)
• 
  Michael Ogbonna Esonu, Asim J. Al-Khalili, Salim Hariri, Dhamin Al-Khalili:
  Design techniques for fault-tolerant systolic arrays. J. VLSI Signal Process. 11(1-2): 151-168 (1995)
• 
  Catherine H. Gebotys:
  An optimal methodology for synthesis of DSP multichip architectures. J. VLSI Signal Process. 11(1-2): 9-19 (1995)
• 
  Yin-Tsung Hwang, Yu Hen Hu:
  A unified partitioning and scheduling scheme for mapping multi-stage regular iterative algorithms onto processor arrays. J. VLSI Signal Process. 11(1-2): 133-150 (1995)
• 
  Kazuhito Ito, Keshab K. Parhi:
  Determining the minimum iteration period of an algorithm. J. VLSI Signal Process. 11(3): 229-244 (1995)
• 
  Hyeong-Kyo Kim, Thomas P. Barnwell III:
  A design synthesis system for recursive DSP algorithms represented by fully specified flow graphs. J. VLSI Signal Process. 11(1-2): 35-50 (1995)
• 
  Chen-Yi Lee, Jer-Min Tsai:
  A shift register architecture for high-speed data sorting. J. VLSI Signal Process. 11(3): 273-280 (1995)
• 
  Nam Ling:
  A special purpose formal verifier for systolic designs in DSP applications. J. VLSI Signal Process. 11(1-2): 169-187 (1995)
• 
  Qutaibah M. Malluhi, Magdy A. Bayoumi, T. R. N. Rao:
  Tree-based special-purpose Array architectures for neural computing. J. VLSI Signal Process. 11(3): 245-262 (1995)
• 
  Marc Pauwels, Gert Goossens, Francky Catthoor, Hugo De Man:
  Formalisation of multi-precision arithmetic for high-level synthesis of DSP architectures. J. VLSI Signal Process. 11(1-2): 97-112 (1995)
• 
  Mirjam Schönfeld, Jens Franzen, Markus Schwiegershausen, Peter Pirsch, Uwe Vehlies, Andreas Münzner:
  The LISA design environment for the synthesis of array processors including memories for the data transfer and fault tolerance by reconfiguration and coding techniques. J. VLSI Signal Process. 11(1-2): 51-74 (1995)
• 
  Ching-Yi Wang, Keshab K. Parhi:
  Resource-constrained loop list scheduler for DSP algorithms. J. VLSI Signal Process. 11(1-2): 75-96 (1995)
• 
  Yoav Yaacoby, Peter R. Cappello:
  Converting affine recurrence equations to quasi-uniform recurrence equations. J. VLSI Signal Process. 11(1-2): 113-131 (1995)