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found 116 matches

• 1984
• 
  William B. Abbott IV:
  Time Specification Conformance of VLSI Test Systems O5. ITC 1984: 105-112
• 
  Vishwani D. Agrawal:
  Will Testability Analysis Replace Fault Simulation ? ITC 1984: 718-718
• 
  Dharma P. Agrawal, Sami A. Al-Arian:
  Comprehensive Fault Model and Testing of CMOS Circuits. ITC 1984: 218-223
• 
  D. P. Ahrens, P. J. Bednarczyk, D. L. Denburg, R. M. Robertson:
  TPG2 : An Automatic Test Program Generator for Custom ICs. ITC 1984: 762-767
• 
  Jeff Angwin, Paul Drake, Glenn Reader:
  The Need for Real-Time Intelligence When Testing VLSI. ITC 1984: 752-761
• 
  Nobuo Arai, Yoshio Yamanaka:
  Parallel Testing of Random Logic LSIs. ITC 1984: 827-833
• 
  Robert W. Atherton, Leonard Ekkelkamp, Chuck Schmitz:
  Logic Device Characterization Using Computer-Aided Test and Analysis. ITC 1984: 367-383
• 
  Arthur Babitz, Kurt Lender:
  Using Simulation in the Design Process - A Case Study. ITC 1984: 229-236
• 
  Ramaswamy Balasubramaniam, Peretz Feder:
  Test Strategy for a 32-Bit Microprocessor Module with Memory Management. ITC 1984: 598-605
• 
  Dean Bandes:
  Exploratory Data Analysis Makes Testing More Valuable for Semiconductor Manufacturing. ITC 1984: 350-358
• 
  Paul H. Bardell, William H. McAnney:
  Parallel Pseudorandom Sequences for Built-In Test. ITC 1984: 302-308
• 
  Catherine Bellon, Gabriele Saucier:
  CADOC : A System for Computer Aided Functional Test. ITC 1984: 680-689
• 
  Catherine Bellon, Raoul Velazco:
  Hardware and Software Tools for Microprocessor Functional Test. ITC 1984: 804-820
• 
  Bhargab B. Bhattacharya, Bidyut Gupta:
  Logical Modeling of Physical Failures and Their Inherent Syndrome Testability in MOS LSI/VLSI Networks. ITC 1984: 847-855
• 
  Dilip K. Bhavsar, Balakrishnan Krishnamurthy:
  Can We Eliminate Fault Escape in Self-Testing by Polynomial Division (Signature Analysis) ? ITC 1984: 134-139
• 
  Gene P. Bosse:
  High Speed Redundancy Processor. ITC 1984: 282-286
• 
  Herb Boulton:
  Design Verification, Product Characterization and Production Testing of Hybrids and Printed Circuit Cards Using High-Sensitivity Thermography Systems. ITC 1984: 747-751
• 
  Saied Bozorgui-Nesbat, Edward J. McCluskey:
  Lower Overhead Design for Testability of Programmable Logic Arrays. ITC 1984: 856-865
• 
  Franc Brglez, Philip Pownall, Robert Hum:
  Applications of Testability Analysis: From ATPG to Critical Delay Path Tracing. ITC 1984: 705-712
• 
  Robert S. Broughton, Michael G. Brashler:
  The Future is Now: Extending CAE into Test of Custom VLSI. ITC 1984: 462-465
• 
  Steve Broyles:
  Automating Functional Programming for Micro-Based Boards. ITC 1984: 730-736
• 
  Anthony J. Burke:
  Software Convergence of Test Program Parameters. ITC 1984: 118-122
• 
  G. Siva Bushanam, Vance R. Harwood, Philip N. King, Roger D. Story:
  Measuring Thermal Rises Due to Digital Device Overdriving. ITC 1984: 400-425
• 
  James F. Campbell Jr.:
  Transfer Function Estimation Part II : Some Experimental Results. ITC 1984: 440-446
• 
  Michael J. Campbell:
  Monitored Burn-In (A Case Study for In-Situ Testing and Reliability Studies). ITC 1984: 518-523
• 
  Stephen Caplow:
  Conquering Testability Problems by Combining In-Circuit and Functional Techniques. ITC 1984: 581-588
• 
  J. Lawrence Carter:
  A Vote in Favor of Fault Simulation. ITC 1984: 719-721
• 
  Harry H. Chen, Robert G. Mathews, John A. Newkirk:
  Test Generation for MOS Circuits. ITC 1984: 70-79
• 
  Brian C. Crosby:
  Adapting CAE Design Information for In-Circuit Test Generation. ITC 1984: 206-211
• 
  Ramaswami Dandapani, Janak H. Patel, Jacob A. Abraham:
  Design of Test Pattern Generators for Built-In Test. ITC 1984: 315-319

skipping 86 more matches