• case-insensitive prefix search: default
  e.g., sig matches "SIGIR" as well as "signal"
• exact word search: append dollar sign ($) to word
  e.g., graph$ matches "graph", but not "graphics"
• boolean and: separate words by space
  e.g., codd model
• boolean or: connect words by pipe symbol (|)
  e.g., graph|network

Update May 7, 2017: Please note that we had to disable the phrase search operator (.) and the boolean not operator (-) due to technical problems. For the time being, phrase search queries will yield regular prefix search result, and search terms preceded by a minus will be interpreted as regular (positive) search terms.

found 32 matches

• 2007
• 
  Ariel Cohen, John W. O'Leary, Amir Pnueli, Mark R. Tuttle, Lenore D. Zuck:
  Verifying Correctness of Transactional Memories. FMCAD 2007: 37-44
• 
  Sara Adams, Magnus Björk, Thomas F. Melham, Carl-Johan H. Seger:
  Automatic Abstraction in Symbolic Trajectory Evaluation. FMCAD 2007: 127-135
• 
  Aaron R. Bradley, Zohar Manna:
  Checking Safety by Inductive Generalization of Counterexamples to Induction. FMCAD 2007: 173-180
• 
  Michael L. Case, Alan Mishchenko, Robert K. Brayton:
  Automated Extraction of Inductive Invariants to Aid Model Checking. FMCAD 2007: 165-172
• 
  Roberto Cavada, Alessandro Cimatti, Anders Franzén, Krishnamani Kalyanasundaram, Marco Roveri, R. K. Shyamasundar:
  Computing Predicate Abstractions by Integrating BDDs and SMT Solvers. FMCAD 2007: 69-76
• 
  Xiaofang Chen, Steven M. German, Ganesh Gopalakrishnan:
  Transaction Based Modeling and Verification of Hardware Protocols. FMCAD 2007: 53-61
• 
  Yan Chen, Yujing He, Fei Xie, Jin Yang:
  Automatic Abstraction Refinement for Generalized Symbolic Trajectory Evaluation. FMCAD 2007: 111-118
• 
  Hana Chockler, Eitan Farchi, Benny Godlin, Sergey Novikov:
  Cross-Entropy Based Testing. FMCAD 2007: 101-108
• 
  Koen Claessen:
  A Coverage Analysis for Safety Property Lists. FMCAD 2007: 139-145
• 
  Kathi Fisler:
  Two-Dimensional Regular Expressions for Compositional Bus Protocols. FMCAD 2007: 154-157
• 
  Alon Flaisher, Alon Gluska, Eli Singerman:
  Case study: Integrating FV and DV in the Verification of the Intel Core^TM 2 Duo Microprocessor. FMCAD 2007: 192-195
• 
  Naghmeh Ghafari, Arie Gurfinkel, Nils Klarlund, Richard J. Trefler:
  Algorithmic Analysis of Piecewise FIFO Systems. FMCAD 2007: 45-52
• 
  Aaron P. Hurst, Alan Mishchenko, Robert K. Brayton:
  Fast Minimum-Register Retiming via Binary Maximum-Flow. FMCAD 2007: 181-187
• 
  Frank Hutter, Domagoj Babic, Holger H. Hoos, Alan J. Hu:
  Boosting Verification by Automatic Tuning of Decision Procedures. FMCAD 2007: 27-34
• 
  Daher Kaiss, Marcelo Skaba, Ziyad Hanna, Zurab Khasidashvili:
  Industrial Strength SAT-based Alignability Algorithm for Hardware Equivalence Verification. FMCAD 2007: 20-26
• 
  Daniel Kroening, Georg Weissenbacher:
  Lifting Propositional Interpolants to the Word-Level. FMCAD 2007: 85-89
• 
  Orna Kupferman, Yoad Lustig:
  What Triggers a Behavior? FMCAD 2007: 146-153
• 
  Yogesh S. Mahajan, Sharad Malik:
  Automating Hazard Checking in Transaction-Level Microarchitecture Models. FMCAD 2007: 62-65
• 
  Martin Oberkönig, Martin Schickel, Hans Eveking:
  A Quantitative Completeness Analysis for Property-Sets. FMCAD 2007: 158-161
• 
  Lee Pike:
  Modeling Time-Triggered Protocols and Verifying Their Real-Time Schedules. FMCAD 2007: 231-238
• 
  Sandip Ray, Jayanta Bhadra:
  A Mechanized Refinement Framework for Analysis of Custom Memories. FMCAD 2007: 239-242
• 
  Neha Rungta, Hyrum Carroll, Eric G. Mercer, Randall J. Roper, Mark J. Clement, Quinn Snell:
  Analyzing Gene Relationships for Down Syndrome with Labeled Transition Graphs. FMCAD 2007: 216-219
• 
  Sean Safarpour, Hratch Mangassarian, Andreas G. Veneris, Mark H. Liffiton, Karem A. Sakallah:
  Improved Design Debugging Using Maximum Satisfiability. FMCAD 2007: 13-19
• 
  Julien Schmaltz:
  A Formal Model of Clock Domain Crossing and Automated Verification of Time-Triggered Hardware. FMCAD 2007: 223-230
• 
  Adrian E. Seigler, Gary A. Van Huben, Hari Mony:
  Formal Verification of Partial Good Self-Test Fencing Structures. FMCAD 2007: 188-191
• 
  Jocelyn Simmonds, Jessica Davies, Arie Gurfinkel, Marsha Chechik:
  Exploiting Resolution Proofs to Speed Up LTL Vacuity Detection for BMC. FMCAD 2007: 3-12
• 
  Edward Smith:
  A Logic for GSTE. FMCAD 2007: 119-126
• 
  Chao Wang, Aarti Gupta, Franjo Ivancic:
  Induction in CEGAR for Detecting Counterexamples. FMCAD 2007: 77-84
• 
  Chao Yan, Mark R. Greenstreet:
  Circuit Level Verification of a High-Speed Toggle. FMCAD 2007: 199-206
• 
  Mohamed H. Zaki, Ghiath Al Sammane, Sofiène Tahar, Guy Bois:
  Combining Symbolic Simulation and Interval Arithmetic for the Verification of AMS Designs. FMCAD 2007: 207-215

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