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ORCIDCarl-Johan H. Seger
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2020 – today
- 2024
[c37]Jeremy Pope, Carl-Johan H. Seger, Henrik Valter:
Higher-order Hardware: Implementation and Evaluation of the Cephalopode Graph Reduction Processor. MEMOCODE 2024: 87-97- 2023
- [c36]Jeremy Pope, Carl-Johan H. Seger:
Bifröst: Creating Hardware With Building Blocks. FDL 2023: 1-8 - 2021
- [c35]Carl-Johan H. Seger:
Formal Verification of Complex Data Paths: An Industrial Experience. FM 2021: 697-716 - 2020
- [c34]Jeremy Pope, Jules Saget, Carl-Johan H. Seger:
Cephalopode: A custom processor aimed at functional language execution for IoT devices. MEMOCODE 2020: 1-6 - [c33]Jeremy Pope, Jules Saget, Carl-Johan H. Seger:
Stately: An FSM Design Tool. MEMOCODE 2020: 1-6
2010 – 2019
- 2017
- [j14]Supratik Chakraborty
, Zurab Khasidashvili, Carl-Johan H. Seger, Rajkumar Gajavelly, Tanmay Haldankar, Dinesh Chhatani, Rakesh Mistry:
Symbolic trajectory evaluation for word-level verification: theory and implementation. Formal Methods Syst. Des. 50(2-3): 317-352 (2017) - 2015
- [c32]Supratik Chakraborty, Zurab Khasidashvili, Carl-Johan H. Seger, Rajkumar Gajavelly, Tanmay Haldankar, Dinesh Chhatani, Rakesh Mistry:
Word-Level Symbolic Trajectory Evaluation. CAV (2) 2015: 128-143 - [i1]Supratik Chakraborty, Zurab Khasidashvili, Carl-Johan H. Seger, Rajkumar Gajavelly, Tanmay Haldankar, Dinesh Chhatani, Rakesh Mistry:
Word-level Symbolic Trajectory Evaluation. CoRR abs/1505.07916 (2015)
2000 – 2009
- 2007
- [c31]Sara Adams, Magnus Björk, Thomas F. Melham, Carl-Johan H. Seger:
Automatic Abstraction in Symbolic Trajectory Evaluation. FMCAD 2007: 127-135 - 2005
- [j13]Carl-Johan H. Seger, Robert B. Jones, John W. O'Leary, Thomas F. Melham, Mark D. Aagaard, Clark W. Barrett, Don Syme:
An industrially effective environment for formal hardware verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(9): 1381-1405 (2005) - 2004
- [c30]Jin Yang, Carl-Johan H. Seger:
Compositional Specification and Model Checking in GSTE. CAV 2004: 216-228 - 2003
- [j12]Jin Yang, Carl-Johan H. Seger:
Introduction to generalized symbolic trajectory evaluation. IEEE Trans. Very Large Scale Integr. Syst. 11(3): 345-353 (2003) - 2002
- [c29]Jin Yang, Carl-Johan H. Seger:
Generalized Symbolic Trajectory Evaluation - Abstraction in Action. FMCAD 2002: 70-87 - 2001
- [j11]Robert B. Jones, John W. O'Leary, Carl-Johan H. Seger, Mark D. Aagaard, Thomas F. Melham:
Practical Formal Verification in Microprocessor Design. IEEE Des. Test Comput. 18(4): 16-25 (2001) - [c28]John Moondanos, Carl-Johan H. Seger, Ziyad Hanna, Daher Kaiss:
CLEVER: Divide and Conquer Combinational Logic Equivalence VERification with False Negative Elimination. CAV 2001: 131-143 - [c27]Jin Yang, Carl-Johan H. Seger:
Introduction to Generalized Symbolic Trajectory Evaluation. ICCD 2001: 360-367 - 2000
- [c26]Carl-Johan H. Seger:
Connecting Bits with Floating-Point Numbers: Model Checking and Theorem Proving in Practice. CADE 2000: 235 - [c25]Mark D. Aagaard, Robert B. Jones, Roope Kaivola, Katherine R. Kohatsu, Carl-Johan H. Seger:
Formal verification of iterative algorithms in microprocessors. DAC 2000: 201-206 - [c24]Mark D. Aagaard, Robert B. Jones, Thomas F. Melham, John W. O'Leary, Carl-Johan H. Seger:
A Methodology for Large-Scale Hardware Verification. FMCAD 2000: 263-282 - [c23]Carl-Johan H. Seger:
Combining functional programming and hardware verification (abstract of invited talk). ICFP 2000: 244
1990 – 1999
- 1999
- [j10]Scott Hazelhurst, Carl-Johan H. Seger:
Model Checking Lattices: Using and reasoning about information orders for abstraction. Log. J. IGPL 7(3): 375-411 (1999) - [c22]Mark D. Aagaard, Robert B. Jones, Carl-Johan H. Seger:
Parametric Representations of Boolean Constraints. DAC 1999: 402-407 - [c21]Mark D. Aagaard, Robert B. Jones, Carl-Johan H. Seger:
Lifted-FL: A Pragmatic Implementation of Combined Model Checking and Theorem Proving. TPHOLs 1999: 323-340 - 1998
- [c20]Mark D. Aagaard, Robert B. Jones, Carl-Johan H. Seger:
Combining Theorem Proving and Trajectory Evaluation in an Industrial Environment. DAC 1998: 538-541 - [c19]Carl-Johan H. Seger:
Formal Methods in CAD from an Industrial Perspective (abstract). FMCAD 1998: 203 - [c18]Carl-Johan H. Seger:
From lattices to practical formal hardware verification. PROCOMET 1998: 3-4 - 1997
- [c17]Scott Hazelhurst, Carl-Johan H. Seger:
Symbolic Trajectory Evaluation. Formal Hardware Verification 1997: 3-78 - 1996
- [c16]Robert B. Jones, Carl-Johan H. Seger, David L. Dill:
Self-Consistency Checking. FMCAD 1996: 159-171 - 1995
- [b1]Janusz A. Brzozowski, Carl-Johan H. Seger:
Asynchronous Circuits. Monographs in Computer Science, Springer 1995, ISBN 978-0-387-94420-3, pp. I-XVI, 1-404 - [j9]Trevor Wing Sang Lee, Mark R. Greenstreet, Carl-Johan H. Seger:
Automatic Verification of Asynchronous Circuits. IEEE Des. Test Comput. 12(1): 24-31 (1995) - [j8]Carl-Johan H. Seger, Randal E. Bryant:
Formal Verification by Symbolic Evaluation of Partially-Ordered Trajectories. Formal Methods Syst. Des. 6(2): 147-189 (1995) - [j7]Scott Hazelhurst, Carl-Johan H. Seger:
A simple theorem prover based on symbolic trajectory evaluation and BDD's. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(4): 413-422 (1995) - [c15]Mark D. Aagaard, Carl-Johan H. Seger:
The formal verification of a pipelined double-precision IEEE floating-point multiplier. ICCAD 1995: 7-10 - 1994
- [j6]Carl-Johan H. Seger, Janusz A. Brzozowski:
Generalized Ternary Simulation of Sequential Circuits. RAIRO Theor. Informatics Appl. 28(3-4): 159-186 (1994) - [c14]Scott Hazelhurst, Carl-Johan H. Seger:
Composing Symbolic Trajectory Evaluation Results. CAV 1994: 273-285 - [c13]Zheng Zhu, Carl-Johan H. Seger:
The Completeness of a Hardware Inference System. CAV 1994: 286-298 - [c12]Trevor Wing Sang Lee, Mark R. Greenstreet, Carl-Johan H. Seger:
Automatic Verification of Refinement. ICCD 1994: 225-229 - [c11]Carl-Johan H. Seger, Randal E. Bryant:
Digital Circuit Verification Using Partially-Ordered State Models. ISMVL 1994: 2-7 - [e1]Jeffrey J. Joyce, Carl-Johan H. Seger:
Higher Order Logic Theorem Proving and its Applications, 6th International Workshop, HUG '93, Vancouver, BC, Canada, August 11-13, 1993, Proceedings. Lecture Notes in Computer Science 780, Springer 1994, ISBN 3-540-57826-9 [contents] - 1993
- [c10]Jeffrey J. Joyce, Carl-Johan H. Seger:
Linking BDD-Based Symbolic Evaluation to Interactive Theorem-Proving. DAC 1993: 469-474 - [c9]Jeffrey J. Joyce, Carl-Johan H. Seger:
The HOL-Voss System: Model-Checking inside a General-Purpose Theorem-Prover. HUG 1993: 185-198 - [c8]Zheng Zhu, Jeffrey J. Joyce, Carl-Johan H. Seger:
Verification of the Tamarack-3 Microprocessor in a Hybrid Verification Environment. HUG 1993: 253-266 - [c7]Sreeranga P. Rajan, Jeffrey J. Joyce, Carl-Johan H. Seger:
From Abstract Data Types to Shift Registers: A Case Study in Formal Specification and Verification at Differing Levels of Abstraction using Theorem Proving and Symbolic Simulation. HUG 1993: 489-500 - 1991
- [j5]Carl-Johan H. Seger:
On the Existence of Speed-Independent Circuits. Theor. Comput. Sci. 86(2): 343-364 (1991) - [c6]Carl-Johan H. Seger, Jeffrey J. Joyce:
A Two-Level Formal Verification Methodology using HOL and COSMOS. CAV 1991: 299-309 - [c5]Randal E. Bryant, Derek L. Beatty, Carl-Johan H. Seger:
Formal Hardware Verification by Symbolic Ternary Trajectory Evaluation. DAC 1991: 397-402 - 1990
- [c4]Randal E. Bryant, Carl-Johan H. Seger:
Formal Verification of Digital Circuits Using Symbolic Ternary System Models. CAV 1990: 33-43 - [c3]Randal E. Bryant, Carl-Johan H. Seger:
Formal Verification of Digital Circuits Using Symbolic Ternary System Models. CAV (DIMACS/AMS volume) 1990: 121-146
1980 – 1989
- 1989
- [j4]Janusz A. Brzozowski, Carl-Johan H. Seger:
A unified framework for race analysis of asynchronous networks. J. ACM 36(1): 20-45 (1989) - [c2]Carl-Johan H. Seger:
A bounded delay race model. ICCAD 1989: 130-133 - 1988
- [j3]Carl-Johan H. Seger, Janusz A. Brzozowski:
An Optimistic Ternary Simulation of Gate Races. Theor. Comput. Sci. 61: 49-66 (1988) - 1987
- [j2]Janusz A. Brzozowski, Carl-Johan H. Seger:
A Characterization of Ternary Simulation of Gate Networks. IEEE Trans. Computers 36(11): 1318-1327 (1987) - 1986
- [j1]David J. Taylor, Carl-Johan H. Seger:
Robust Storage Structures for Crash Recovery. IEEE Trans. Computers 35(4): 288-295 (1986) - [c1]Janusz A. Brzozowski, Carl-Johan H. Seger:
Correspondence between Ternary Simulation and Binary Race Analysis in Gate Networks (Extended Summary). ICALP 1986: 69-78
Coauthor Index
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