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ORCIDJulien Schmaltz
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2020 – today
- 2021
[b1]Jan Friso Groote
, Rolf Morel, Julien Schmaltz, Adam Watkins:
Logic Gates, Circuits, Processors, Compilers and Computers. Springer 2021, ISBN 978-3-030-68552-2, pp. 1-193- 2020
- [c41]Alexander Fedotov, Jeroen J. A. Keiren, Julien Schmaltz:
Effective System Level Liveness Verification. FMCAD 2020: 7-15
2010 – 2019
- 2018
- [c40]Perry van Wesel, Julien Schmaltz:
Formal micro-architectural analysis of on-chip ring networks. DAC 2018: 94:1-94:6 - [c39]Alexander Fedotov, Julien Schmaltz:
Automatic generation of hardware checkers from formal micro-architectural specifications. DATE 2018: 1568-1573 - 2016
- [c38]Ruud Koolen, Julien Schmaltz:
Modeling Information Routing with Noninterference. MILS@HiPEAC 2016 - 2015
- [c37]Sebastiaan J. C. Joosten, Julien Schmaltz:
Automatic extraction of micro-architectural models of communication fabrics from register transfer level designs. DATE 2015: 1413-1418 - [c36]Ruud Koolen, Julien Schmaltz:
Formal Methods for MILS: Formalisations of the GWV Firewall. MILS@HiPEAC 2015 - [c35]Sanne Wouda, Sebastiaan J. C. Joosten, Julien Schmaltz:
Process algebra semantics & reachability analysis for micro-architectural models of communication fabrics. MEMOCODE 2015: 198-207 - [c34]Freek Verbeek, Oto Havle, Julien Schmaltz, Sergey Tverdyshev, Holger Blasum, Bruno Langenstein, Werner Stephan, Burkhart Wolff, Yakoub Nemouchi:
Formal API Specification of the PikeOS Separation Kernel. NFM 2015: 375-389 - 2014
- [j11]Freek Verbeek, Sergey Tverdyshev, Oto Havle, Holger Blasum, Bruno Langenstein, Werner Stephan, Yakoub Nemouchi, Abderrahmane Feliachi, Burkhart Wolff, Julien Schmaltz:
Formal Specification of a Generic Separation Kernel. Arch. Formal Proofs 2014 (2014) - [j10]Freek Verbeek, Julien Schmaltz:
A Decision Procedure for Deadlock-Free Routing in Wormhole Networks. IEEE Trans. Parallel Distributed Syst. 25(8): 1935-1944 (2014) - [c33]Sebastiaan J. C. Joosten, Julien Schmaltz:
Scalable liveness verification for communication fabrics. DATE 2014: 1-6 - [c32]Adrian Garcia Ramirez, Julien Schmaltz, Freek Verbeek, Bruno Langenstein, Holger Blasum:
On Two Models of Noninterference: Rushby and Greve, Wilding, and Vanfleet. SAFECOMP 2014: 246-261 - [c31]Bernard van Gastel, Freek Verbeek, Julien Schmaltz:
Inference of channel types in micro-architectural models of on-chip communication networks. VLSI-SoC 2014: 1-6 - [e3]Freek Verbeek, Julien Schmaltz:
Proceedings Twelfth International Workshop on the ACL2 Theorem Prover and its Applications, Vienna, Austria, 12-13th July 2014. EPTCS 152, 2014 [contents] - 2013
- [c30]Freek Verbeek, Sebastiaan J. C. Joosten, Julien Schmaltz:
Formal Deadlock Verification for Click Circuits. ASYNC 2013: 183-190 - [c29]Sebastiaan J. C. Joosten, Julien Schmaltz:
Generation of inductive invariants from register transfer level designs of communication fabrics. MEMOCODE 2013: 57-64 - [c28]Sebastiaan J. C. Joosten, Bernard van Gastel, Julien Schmaltz:
A Macro for Reusing Abstract Functions and Theorems. ACL2 2013: 29-41 - [c27]Freek Verbeek, Julien Schmaltz:
Verification of Building Blocks for Asynchronous Circuits. ACL2 2013: 70-84 - [c26]Bernard van Gastel, Julien Schmaltz:
A formalisation of XMAS. ACL2 2013: 111-126 - 2012
- [j9]Freek Verbeek, Julien Schmaltz:
Proof Pearl: A Formal Proof of Dally and Seitz' Necessary and Sufficient Condition for Deadlock-Free Routing in Interconnection Networks. J. Autom. Reason. 48(4): 419-439 (2012) - [j8]Faranak Heidarian, Julien Schmaltz, Frits W. Vaandrager:
Analysis of a clock synchronization protocol for wireless sensor networks. Theor. Comput. Sci. 413(1): 87-105 (2012) - [j7]Freek Verbeek, Julien Schmaltz:
Easy Formal Specification and Validation of Unbounded Networks-on-Chips Architectures. ACM Trans. Design Autom. Electr. Syst. 17(1): 1:1-1:28 (2012) - [j6]Freek Verbeek, Julien Schmaltz:
Towards the formal verification of cache coherency at the architectural level. ACM Trans. Design Autom. Electr. Syst. 17(3): 20:1-20:16 (2012) - [c25]Freek Verbeek, Julien Schmaltz:
Automatic generation of deadlock detection algorithms for a family of microarchitecture description languages of communication fabrics. HLDVT 2012: 25-32 - [c24]Abdulaziz Alhussien, Nader Bagherzadeh, Freek Verbeek, Bernard van Gastel, Julien Schmaltz:
A formally verified deadlock-free routing function in a fault-tolerant NoC architecture. SBCCI 2012: 1-6 - 2011
- [j5]Freek Verbeek, Julien Schmaltz:
A Comment on "A Necessary and Sufficient Condition for Deadlock-Free Adaptive Routing in Wormhole Networks". IEEE Trans. Parallel Distributed Syst. 22(10): 1775-1776 (2011) - [j4]Freek Verbeek, Julien Schmaltz:
On Necessary and Sufficient Conditions for Deadlock-Free Routing in Wormhole Networks. IEEE Trans. Parallel Distributed Syst. 22(12): 2022-2032 (2011) - [c23]Freek Verbeek, Julien Schmaltz:
Hunting deadlocks efficiently in microarchitectural models of communication fabrics. FMCAD 2011: 223-231 - [c22]Carsten Rütz, Julien Schmaltz:
An Experience Report on an Industrial Case-Study about Timed Model-Based Testing with UPPAAL-TRON. ICST Workshops 2011: 39-46 - [c21]Freek Verbeek, Julien Schmaltz:
Automatic verification for deadlock in networks-on-chips with adaptive routing and wormhole switching. NOCS 2011: 25-32 - [c20]Freek Verbeek, Julien Schmaltz:
A Fast and Verified Algorithm for Proving Store-and-Forward Networks Deadlock-Free. PDP 2011: 3-10 - [c19]Freek Verbeek, Julien Schmaltz:
Formal verification of a deadlock detection algorithm. ACL2 2011: 103-112 - [e2]Marko C. J. D. van Eekelen, Herman Geuvers, Julien Schmaltz, Freek Wiedijk:
Interactive Theorem Proving - Second International Conference, ITP 2011, Berg en Dal, The Netherlands, August 22-25, 2011. Proceedings. Lecture Notes in Computer Science 6898, Springer 2011, ISBN 978-3-642-22862-9 [contents] - [e1]David S. Hardin, Julien Schmaltz:
Proceedings 10th International Workshop on the ACL2 Theorem Prover and its Applications, ACL2 2011, Austin, Texas, USA, November 3-4, 2011. EPTCS 70, 2011 [contents] - [i1]Julien Schmaltz:
Formal verification of a time-triggered hardware interface. CoRR abs/1103.2246 (2011) - 2010
- [j3]Jasper Berendsen, David N. Jansen, Julien Schmaltz, Frits W. Vaandrager:
The axiomatization of override and update. J. Appl. Log. 8(1): 141-150 (2010) - [c18]Freek Verbeek, Julien Schmaltz:
Formal specification of networks-on-chips: deadlock and evacuation. DATE 2010: 1701-1706 - [c17]Sabrina von Styp, Henrik C. Bohnenkamp, Julien Schmaltz:
A Conformance Testing Relation for Symbolic Timed Automata. FORMATS 2010: 243-255 - [c16]Fides Aarts, Julien Schmaltz, Frits W. Vaandrager:
Inference and Abstraction of the Biometric Passport. ISoLA (1) 2010: 673-686 - [c15]Freek Verbeek, Julien Schmaltz:
A Formal Proof of a Necessary and Sufficient Condition for Deadlock-Free Adaptive Networks. ITP 2010: 67-82
2000 – 2009
- 2009
- [j2]Dominique Borrione, Amr Helmy, Laurence Pierre, Julien Schmaltz:
A Formal Approach to the Verification of Networks on Chip. EURASIP J. Embed. Syst. 2009 (2009) - [c14]Faranak Heidarian, Julien Schmaltz, Frits W. Vaandrager:
Analysis of a Clock Synchronization Protocol for Wireless Sensor Networks. FM 2009: 516-531 - [c13]Tom van den Broek, Julien Schmaltz:
Towards a formally verified network-on-chip. FMCAD 2009: 184-187 - [c12]Wojciech Mostowski, Erik Poll, Julien Schmaltz, Jan Tretmans, Ronny Wichers Schreur:
Model-Based Testing of Electronic Passports. FMICS 2009: 207-209 - 2008
- [j1]Julien Schmaltz, Dominique Borrione:
A functional formalization of on chip communications. Formal Aspects Comput. 20(3): 241-258 (2008) - [c11]Julien Schmaltz, Jan Tretmans:
On Conformance Testing for Timed Systems. FORMATS 2008: 250-264 - [c10]Dominique Borrione, Amr Helmy, Laurence Pierre, Julien Schmaltz:
Executable formal specification and validation of NoC communication infrastructures. SBCCI 2008: 176-181 - 2007
- [c9]Julien Schmaltz:
A Formal Model of Clock Domain Crossing and Automated Verification of Time-Triggered Hardware. FMCAD 2007: 223-230 - [c8]Dominique Borrione, Amr Helmy, Laurence V. Pierre, Julien Schmaltz:
A Generic Model for Formally Verifying NoC Communication Architectures: A Case Study. NOCS 2007: 127-136 - 2006
- [c7]Julien Schmaltz, Dominique Borrione:
Towards a formal theory of on chip communications in the ACL2 logic. ACL2 2006: 47-56 - [c6]Julien Schmaltz, Dominique Borrione:
Formalizing On Chip Communications in a Functional Style. Trustworthy Software 2006 - [c5]Julien Schmaltz:
A Formal Model of Lower System Layers. FMCAD 2006: 191-192 - 2005
- [c4]Julien Schmaltz, Dominique Borrione:
A Generic Network on Chip Model. TPHOLs 2005: 310-325 - 2004
- [c3]Julien Schmaltz, Dominique Borrione:
A Functional Approach to the Formal Specification of Networks on Chip. FMCAD 2004: 52-66 - [c2]Ghiath Al Sammane, Julien Schmaltz, Diana Toma, Pierre Ostier, Dominique Borrione:
TheoSim: combining symbolic simulation and theorem proving for hardware verification. SBCCI 2004: 60-65 - 2003
- [c1]Ghiath Al Sammane, Diana Toma, Julien Schmaltz, Pierre Ostier, Dominique Borrione:
Constrained Symbolic Simulation with Mathematica and ACL2. CHARME 2003: 150-157
Coauthor Index
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