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Publication search results
found 113 matches
- 2011
- Ali Abbasinasab, Mehdi Mohammadi, Siamak Mohammadi, Svetlana N. Yanushkevich, Michael Smith:
Mutant Fault Injection in Functional Properties of a Model to Improve Coverage Metrics. DSD 2011: 422-425 - Nima Aghaee, Zebo Peng, Petru Eles:
Adaptive Temperature-Aware SoC Test Scheduling Considering Process Variation. DSD 2011: 197-204 - Ignacio Algredo-Badillo, Claudia Feregrino Uribe, René Cumplido, Miguel Morales-Sandoval:
Novel Hardware Architecture for Implementing the Inner Loop of the SHA-2 Algorithms. DSD 2011: 543-549 - Ahmet Aris, Siddika Berna Örs, Gökay Saldamli:
Architectures for Fast Modular Multiplication. DSD 2011: 434-437 - Muhammad Awais, Ashwani Singh, Emmanuel Boutillon, Guido Masera:
A Novel Architecture for Scalable, High Throughput, Multi-standard LDPC Decoder. DSD 2011: 340-347 - Yu Bai, Weidong Kuang:
Design of Asynchronous Circuits on FPGAs for Soft Error Tolerance. DSD 2011: 247-253 - Jiri Balcarek, Petr Fiser, Jan Schmidt:
Techniques for SAT-Based Constrained Test Pattern Generation. DSD 2011: 360-366 - Alessandro Bardine, Pierfrancesco Foglia, Francesco Panicucci, Marco Solinas, Julio Sahuquillo:
Energy Behaviour of NUCA Caches in CMPs. DSD 2011: 746-753 - Alessandro Barenghi, Guido Bertoni, Fabrizio De Santis, Filippo Melzani:
On the Efficiency of Design Time Evaluation of the Resistance to Power Attacks. DSD 2011: 777-785 - Charly Bechara, Nicolas Ventroux, Daniel Etiemble:
Comparison of Different Thread Scheduling Strategies for Asymmetric Chip MultiThreading Architectures in Embedded Systems. DSD 2011: 181-187 - Nicola Bombieri, Franco Fummi, Sara Vinco, Davide Quaglia:
Automatic Interface Generation for Component Reuse in HW-SW Partitioning. DSD 2011: 793-796 - Jaroslav Borecký, Martin Kohlík, Pavel Kubalík, Hana Kubátová:
Fault Models Usability Study for On-line Tested FPGA. DSD 2011: 287-290 - Michal Bryk, Lech Józwiak, Wieslaw Kuzmicz:
Rapid and Accurate Leakage Power Estimation for Nano-CMOS Circuits. DSD 2011: 685-692 - Jesús Camacho Villanueva, José Flich, José Duato, Hans Eberle, Wladek Olesinski:
Towards an Efficient NoC Topology through Multiple Injection Ports. DSD 2011: 165-172 - Jean-Michel Chabloz, Ahmed Hemani:
Low-Latency and Low-Overhead Mesochronous and Plesiochronous Synchronizers. DSD 2011: 157-164 - Karthik Chandrasekar, Benny Akesson, Kees Goossens:
Improved Power Modeling of DDR SDRAMs. DSD 2011: 99-108 - Jiaoyan Chen, Dilip P. Vasudevan, Emanuel M. Popovici, Michel P. Schellekens:
Design of a Low Power, Sub-Threshold, Asynchronous Arithmetic Logic Unit Using a Bidirectional Adder. DSD 2011: 301-308 - Junfeng Chu, Mohammed Benaissa:
A Novel Architecture of Implementing Error Detecting AES Using PRNS. DSD 2011: 667-673 - Hadrien A. Clarke, Kazuaki J. Murakami:
Thermal Effect of TSVs in 3D Die-Stacked Integrated Circuits. DSD 2011: 503-508 - Morteza Damavandpeyma, Sander Stuijk, Twan Basten, Marc Geilen, Henk Corporaal:
Hybrid Code-Data Prefetch-Aware Multiprocessor Task Graph Scheduling. DSD 2011: 583-590 - Giovanni Danese, Francesco Leporati, Alessandra Majani, Giulia Matrone, Enrico Merlino:
A Wearable Intelligent System for the Health of Expectant Mom's and of Their Children. DSD 2011: 757-763 - Luka B. Daoud, Mohamed El-Sayed Ragab, Victor Goulart:
Faster Processor Allocation Algorithms for Mesh-Connected CMPs. DSD 2011: 805-808 - Rohit Datta, Gerhard P. Fettweis, Zsolt Kollár, Péter Horváth:
FBMC and GFDM Interference Cancellation Schemes for Flexible Digital Radio PHY Design. DSD 2011: 335-339 - Mehdi Dehbashi, André Sülflow, Görschwin Fey:
Automated Design Debugging in a Testbench-Based Verification Environment. DSD 2011: 479-486 - Roland Dobai, Marcel Baláz:
SAT-Based Generation of Compressed Skewed-Load Tests for Transition Delay Faults. DSD 2011: 191-196 - Václav Dvorák, Petr Mikusek:
On the Cascade Implementation of Multiple-Output Sparse Logic Functions. DSD 2011: 21-28 - Constantinos Efstathiou, Kiamal Z. Pekmestzi, Nicholas Axelos:
On the Design of Modulo 2n+1 Multipliers. DSD 2011: 453-459 - Leandro Fiorin, Laura Micconi, Mariagiovanna Sami:
Design of Fault Tolerant Network Interfaces for NoCs. DSD 2011: 393-400 - Farshad Firouzi, Amir Yazdanbakhsh, Hamed Dorosti, Sied Mehdi Fakhraie:
Dynamic Soft Error Hardening via Joint Body Biasing and Dynamic Voltage Scaling. DSD 2011: 385-392 - Martti Forsell, Ville Leppänen, Martti Penttonen:
Cost of Sparse Mesh Layouts Supporting Throughput Computing. DSD 2011: 316-323
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