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ORCIDIgnacio Algredo-Badillo
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2020 – today
- 2024
[j21]Jose Misael Burruel-Zazueta, Héctor Rodríguez Rangel, Gloria Ekaterine Peralta-Peñuñuri, Vicenç Puig Cayuela, Ignacio Algredo-Badillo, Luis Alberto Morales-Rosales:
Biometric lock with facial recognition implemented with deep learning techniques. Comput. Sci. Inf. Syst. 21(4): 1359-1387 (2024)- 2023
- [c9]Monserrat Vázquez-Hernández, Ignacio Algredo-Badillo, Luis Alberto Morales-Rosales, Luis Villaseñor Pineda:
White-Box Adversarial Attacks Against Sentiment-Analysis Models using an Aspect-Based Approach. CISETC 2023: 601-617 - 2022
- [j20]Ignacio Algredo-Badillo, Germàn Portillo-García, Kelsey A. Ramírez-Gutiérrez, Luis Alberto Morales-Rosales:
Irregularities recognition system for automotive pieces. Int. J. Comput. Vis. Robotics 12(6): 614-631 (2022) - [j19]Alan Torres-Alvarado
, Luis Alberto Morales-Rosales, Ignacio Algredo-Badillo, Francisco López-Huerta, Mariana Lobato Báez, Juan Carlos López Pimentel:
Trade-Off Analysis of Hardware Architectures for Channel-Quality Classification Models. Sensors 22(7): 2497 (2022) - [j18]Alan Torres-Alvarado, Luis Alberto Morales-Rosales, Ignacio Algredo-Badillo, Francisco López-Huerta, Mariana Lobato Báez, Juan Carlos López Pimentel:
An SHA-3 Hardware Architecture against Failures Based on Hamming Codes and Triple Modular Redundancy. Sensors 22(8): 2985 (2022) - [j17]Ignacio Algredo-Badillo, Miguel Morales-Sandoval, Alejandro Medina-Santiago, Carlos Arturo Hernández-Gracidas, Mariana Lobato Báez, Luis Alberto Morales-Rosales:
A SHA-256 Hybrid-Redundancy Hardware Architecture for Detecting and Correcting Errors. Sensors 22(13): 5028 (2022) - 2021
- [j16]Daniel Pacheco Bautista, Ricardo Carreño Aguilera, Francisco Aguilar Acevedo, Ignacio Algredo-Badillo:
Bit-Vector-Based Hardware Accelerator for DNA Alignment Tools. J. Circuits Syst. Comput. 30(5): 2150087:1-2150087:19 (2021) - [j15]Miguel Morales-Sandoval, Luis Armando Rodriguez Flores, René Cumplido, Jose Juan Garcia-Hernandez, Claudia Feregrino, Ignacio Algredo-Badillo:
A Compact FPGA-Based Accelerator for Curve-Based Cryptography in Wireless Sensor Networks. J. Sensors 2021: 8860413:1-8860413:13 (2021) - [j14]Ignacio Algredo-Badillo, Kelsey A. Ramírez-Gutiérrez, Luis Alberto Morales-Rosales, Daniel Pacheco Bautista, Claudia Feregrino Uribe:
Hybrid Pipeline Hardware Architecture Based on Error Detection and Correction for AES. Sensors 21(16): 5655 (2021) - [j13]Alejandro Medina-Santiago, Carlos Arturo Hernández-Gracidas, Luis Alberto Morales-Rosales, Ignacio Algredo-Badillo, Monica Amador García, Jorge Antonio Orozco Torres:
CMOS Implementation of ANNs Based on Analog Optimization of N-Dimensional Objective Functions. Sensors 21(21): 7071 (2021) - 2020
- [j12]Luis Alberto Morales-Rosales, Ignacio Algredo-Badillo, Mariana Lobato Báez, Carlos Arturo Hernández-Gracidas, Héctor Rodríguez Rangel:
A fuzzy petri net model for assessing analogical reasoning in children ranging from 5 to 8 years old. J. Intell. Fuzzy Syst. 39(5): 7161-7175 (2020) - [j11]Juan Carlos Carrillo-Alarcón, Luis Alberto Morales-Rosales, Héctor Rodríguez Rangel, Mariana Lobato Báez, Antonio Muñoz, Ignacio Algredo-Badillo:
A Metaheuristic Optimization Approach for Parameter Estimation in Arrhythmia Classification from Unbalanced Data. Sensors 20(11): 3139 (2020)
2010 – 2019
- 2019
- [j10]Alejandro Medina-Santiago, Mario Alfredo Reyes-Barranca, Ignacio Algredo-Badillo, Alfonso Martinez Cruz, Kelsey A. Ramírez-Gutiérrez, Eleazar Adrián Cortés-Barrón:
Reconfigurable arithmetic logic unit designed with threshold logic gates. IET Circuits Devices Syst. 13(1): 21-30 (2019) - [j9]Ignacio Algredo-Badillo, Luis Alberto Morales-Rosales, Carlos Arturo Hernández-Gracidas, Juan C. Cruz-Victoria, Daniel Pacheco Bautista, Miguel Morales-Sandoval:
Real time FPGA-ANN architecture for outdoor obstacle detection focused in road safety. J. Intell. Fuzzy Syst. 36(5): 4425-4436 (2019) - 2018
- [j8]Ignacio Algredo-Badillo, Francisco Rubén Castillo Soria, Kelsey A. Ramírez-Gutiérrez, Luis Alberto Morales-Rosales, Alejandro Medina-Santiago, Claudia Feregrino Uribe:
Lightweight Security Hardware Architecture Using DWT and AES Algorithms. IEICE Trans. Inf. Syst. 101-D(11): 2754-2761 (2018) - [j7]Luis Alberto Morales-Rosales, Ignacio Algredo-Badillo, Carlos Arturo Hernández-Gracidas, Héctor Rodríguez Rangel, Mariana Lobato Báez:
On-road obstacle detection video system for traffic accident prevention. J. Intell. Fuzzy Syst. 35(1): 533-547 (2018) - 2017
- [c8]Luis Armando Rodriguez Flores, Miguel Morales-Sandoval, René Cumplido, Claudia Feregrino Uribe, Ignacio Algredo-Badillo:
A compact FPGA-based microcoded coprocessor for exponentiation in asymmetric encryption. LASCAS 2017: 1-4 - 2015
- [c7]M. A. Saldaña-O., Luis Enrique Ramos Velasco, J. P. Ordaz-O., Abel García-Barrientos, Ignacio Algredo-Badillo, Jean-François Balmat, Frédéric Lafont:
A comparative study of the wavenet PID controllers for applications in non-linear systems. CCE 2015: 1-6 - 2014
- [j6]Rommel García, Ignacio Algredo-Badillo, Miguel Morales-Sandoval, Claudia Feregrino Uribe, René Cumplido:
A compact FPGA-based processor for the Secure Hash Algorithm SHA-256. Comput. Electr. Eng. 40(1): 194-202 (2014) - 2013
- [j5]Ignacio Algredo-Badillo, Claudia Feregrino Uribe, René Cumplido, Miguel Morales-Sandoval:
FPGA-based implementation alternatives for the inner loop of the Secure Hash Algorithm SHA-256. Microprocess. Microsystems 37(6-7): 750-757 (2013) - [c6]Eduardo Cuevas-Farfan, Miguel Morales-Sandoval, René Cumplido, Claudia Feregrino Uribe, Ignacio Algredo-Badillo:
A programmable FPGA-based cryptoprocessor for bilinear pairings over F2m. ReCoSoC 2013: 1-8 - 2012
- [c5]Ignacio Algredo-Badillo, Miguel Morales-Sandoval, Claudia Feregrino Uribe, René Cumplido:
Throughput and Efficiency Analysis of Unrolled Hardware Architectures for the SHA-512 Hash Algorithm. ISVLSI 2012: 63-68 - [i2]Francisco Rubén Castillo Soria, Gustavo Fernández Torres, Ignacio Algredo-Badillo:
A Lossless Data Hiding Technique based on AES-DWT. CoRR abs/1212.2669 (2012) - [i1]Ernesto Cortés Pérez, Ignacio Algredo-Badillo, Víctor Hugo García Rodríguez:
Performance Analysis of ANFIS in short term Wind Speed Prediction. CoRR abs/1212.2671 (2012) - 2011
- [c4]Ignacio Algredo-Badillo, Claudia Feregrino Uribe, René Cumplido, Miguel Morales-Sandoval:
Novel Hardware Architecture for Implementing the Inner Loop of the SHA-2 Algorithms. DSD 2011: 543-549 - 2010
- [j4]Ignacio Algredo-Badillo, Claudia Feregrino Uribe, René Cumplido, Miguel Morales-Sandoval:
Efficient hardware architecture for the AES-CCM protocol of the IEEE 802.11i standard. Comput. Electr. Eng. 36(3): 565-577 (2010) - [j3]Miguel Morales-Sandoval, Claudia Feregrino Uribe, René Cumplido, Ignacio Algredo-Badillo:
A Single Formula and its Implementation in FPGA for Elliptic Curve Point Addition Using Affine Representation. J. Circuits Syst. Comput. 19(2): 425-433 (2010)
2000 – 2009
- 2009
- [j2]Miguel Morales-Sandoval, Claudia Feregrino Uribe, René Cumplido, Ignacio Algredo-Badillo:
An area/performance trade-off analysis of a GF(2m) multiplier architecture for elliptic curve cryptography. Comput. Electr. Eng. 35(1): 54-58 (2009) - [c3]Miguel Morales-Sandoval, Claudia Feregrino Uribe, René Cumplido, Ignacio Algredo-Badillo:
A Run Time Reconfigurable Co-processor for Elliptic Curve Scalar Multiplication. ENC 2009: 345-350 - 2008
- [j1]Ignacio Algredo-Badillo, Claudia Feregrino Uribe, René Cumplido, Miguel Morales-Sandoval:
Design and Implementation of a Non-pipelined MD5 Hardware Architecture Using a New Functional Description. IEICE Trans. Inf. Syst. 91-D(10): 2519-2523 (2008) - [c2]Ignacio Algredo-Badillo, Claudia Feregrino Uribe, René Cumplido, Miguel Morales-Sandoval:
FPGA Implementation and Performance Evaluation of AES-CCM Cores for Wireless Networks. ReConFig 2008: 421-426 - 2006
- [c1]Ignacio Algredo-Badillo, Claudia Feregrino Uribe, René Cumplido:
Design and Implementation of an FPGA-Based 1.452-Gbps Non-pipelined AES Architecture. ICCSA (3) 2006: 456-465
Coauthor Index
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