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2020 – today
- 2022
[c20]Ondrej Kachman, Jakub Findura, Marcel Baláz, Gábor Gyepes, Libor Majer, Marian Vojs:
Intelligent Monitoring System for Universal Data Collection and Analysis. RADIOELEKTRONIKA 2022: 1-6- 2020
- [c19]Ondrej Kachman, Marcel Baláz:
Efficient Patch Module for Single-bank or Dual-bank Firmware Updates for Embedded Devices. DDECS 2020: 1-6
2010 – 2019
- 2019
- [j4]Ondrej Kachman, Marcel Baláz, Peter Malík
:
Universal framework for remote firmware updates of low-power devices. Comput. Commun. 139: 91-102 (2019) - 2018
- [j3]Stefan Kristofík, Marcel Baláz, Peter Malík:
Hardware redundancy architecture based on reconfigurable logic blocks with persistent high reliability improvement. Microelectron. Reliab. 86: 38-53 (2018) - 2017
- [c18]Ondrej Kachman, Marcel Baláz:
Firmware Update Manager: A remote firmware reprogramming tool for low-power devices. DDECS 2017: 88-91 - [c17]Ondrej Kachman, Marcel Baláz:
Configurable Reprogramming Methodology for Embedded Low-Power Devices. DoCEIS 2017: 211-219 - 2016
- [c16]Stefan Kristofík, Marcel Baláz:
Built-in self-repair architecture generator for digital cores. DDECS 2016: 138-143 - [c15]Ondrej Kachman, Marcel Baláz:
Optimized differencing algorithm for firmware updates of low-power devices. DDECS 2016: 227-230 - [c14]Ondrej Kachman, Marcel Baláz:
Effective Over-the-Air Reprogramming for Low-Power Devices in Cyber-Physical Systems. DoCEIS 2016: 284-292 - 2015
- [c13]Stefan Kristofík, Marcel Baláz, Mária Fischerová:
Generic Self Repair Architecture with On-Line Fault Diagnosis. DDECS 2015: 279-282 - [c12]Marcel Baláz, Stefan Kristofík:
Generic Self Repair Architecture with Multiple Fault Handling Capability. DSD 2015: 197-204 - 2014
- [c11]Marcel Baláz, Stefan Kristofík, Mária Fischerová:
Generic built-in self-repair architectures for SoC logic cores. DDECS 2014: 45-50 - [c10]Andrej Kincel, Marcel Baláz:
Case study: BISR for a processor multiplier. DDECS 2014: 314-317 - 2013
- [j2]Roland Dobai, Marcel Baláz:
Compressed Skewed-Load Delay Test Generation Based on Evolution and Deterministic Initialization of Populations. Comput. Informatics 32(2): 251-272 (2013) - [j1]Roland Dobai, Marcel Baláz:
SAT-based generation of compressed skewed-load tests for transition delay faults. Microprocess. Microsystems 37(2): 196-205 (2013) - [c9]Andrej Kincel, Marcel Baláz:
MBIST for LEON3 processor core cache. DDECS 2013: 287-288 - 2012
- [c8]Roland Dobai, Marcel Baláz:
Genetic method for compressed skewed-load delay test generation. DDECS 2012: 242-247 - [c7]Roland Dobai, Marcel Baláz, Mária Fischerová:
Automated Generation of Built-In Self-Repair Architectures for Random Logic SoC Cores. DSD 2012: 73-78 - 2011
- [c6]Roland Dobai, Marcel Baláz:
SAT-Based Generation of Compressed Skewed-Load Tests for Transition Delay Faults. DSD 2011: 191-196
2000 – 2009
- 2009
- [c5]Peter Malík, Michal Ufnal, Arkadiusz W. Luczyk, Marcel Baláz, Witold A. Pleskacz:
MDCT / IMDCT low power implementations in 90 nm CMOS technology for MP3 audio. DDECS 2009: 144-147 - 2008
- [c4]Peter Malík, Marcel Baláz, Martin Simlastík, Arkadiusz W. Luczyk, Witold A. Pleskacz:
Various MDCT implementations in 0.35µm CMOS. DDECS 2008: 170-173 - 2007
- [c3]Peter Malík, Marcel Baláz, Tomás Pikula, Martin Simlastík:
An Improved MDCT IP Core Generator with Architectural Model Simulation. DDECS 2007: 193-198 - 2006
- [c2]Martin Simlastík, Peter Malík, Tomás Pikula, Marcel Baláz:
FPGA Implementation of a Fast MDCT Algorithm. DDECS 2006: 228-229 - [c1]Peter Malík, Marcel Baláz, Tomás Pikula, Martin Simlastík:
MDCT IP Core Generator with Architectural Model Simulation. VLSI-SoC 2006: 18-23
Coauthor Index
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