• case-insensitive prefix search: default
  e.g., sig matches "SIGIR" as well as "signal"
• exact word search: append dollar sign ($) to word
  e.g., graph$ matches "graph", but not "graphics"
• boolean and: separate words by space
  e.g., codd model
• boolean or: connect words by pipe symbol (|)
  e.g., graph|network

Update May 7, 2017: Please note that we had to disable the phrase search operator (.) and the boolean not operator (-) due to technical problems. For the time being, phrase search queries will yield regular prefix search result, and search terms preceded by a minus will be interpreted as regular (positive) search terms.

found 18 matches

• 2017
• 
  Yang Zhang, Haipeng Zha, Vaishnavi Sahir, Huimei Cheng, Peter A. Beerel:
  Test Margin and Yield in Bundled Data and Ring-Oscillator Based Designs. ASYNC 2017: 85-93
• 
  Ameer M. S. Abdelhadi, Mark R. Greenstreet:
  Interleaved Architectures for High-Throughput Synthesizable Synchronization FIFOs. ASYNC 2017: 41-48
• 
  Jordi Cortadella, Alberto Moreno, Danil Sokolov, Alex Yakovlev, David Lloyd:
  Waveform Transition Graphs: A Designer-Friendly Formalism for Asynchronous Behaviours. ASYNC 2017: 73-74
• 
  Johnson Fernandes, Danil Sokolov, Alex Yakovlev:
  Elastic Bundles: Modelling and Synthesis of Asynchronous Circuits with Granular Rigidity. ASYNC 2017: 57-64
• 
  Matthias Függer, Attila Kinali, Christoph Lenzen, Thomas Polzer:
  Metastability-Aware Memory-Efficient Time-to-Digital Converters. ASYNC 2017: 49-56
• 
  Weiwei Jiang, Steven M. Nowick:
  A High-Throughput Asynchronous Multi-resource Arbiter Using a Pipelined Assignment Approach. ASYNC 2017: 1-9
• 
  Victor Khomenko, Danil Sokolov, Andrey Mokhov, Alex Yakovlev:
  WAITX: An Arbiter for Non-persistent Signals. ASYNC 2017: 33-40
• 
  Rajit Manohar, Yoram Moses:
  The Eventual C-Element Theorem for Delay-Insensitive Asynchronous Circuits. ASYNC 2017: 102-109
• 
  Gabriele Miorandi, Marco Balboni, Steven M. Nowick, Davide Bertozzi:
  Accurate Assessment of Bundled-Data Asynchronous NoCs Enabled by a Predictable and Efficient Hierarchical Synthesis Flow. ASYNC 2017: 10-17
• 
  Alberto Moreno, Jordi Cortadella:
  Synthesis of All-Digital Delay Lines. ASYNC 2017: 75-82
• 
  Robert Najvirt, Thomas Polzer, Andreas Steininger:
  Measuring Metastability with Free-Running Clocks. ASYNC 2017: 18-24
• 
  Naoya Onizawa, Masashi Imai, Takahiro Hanyu, Tomohiro Yoneda:
  MTJ-based Asynchronous Circuits for Re-initialization Free Computing against Power Failures. ASYNC 2017: 118-125
• 
  Chun-Hong Shih, Jie-Hong R. Jiang:
  Criticality and Sensitivity Analysis for Incremental Performance Optimization of Asynchronous Pipelines. ASYNC 2017: 94-101
• 
  Jean Simatic, Abdelkarim Cherkaoui, François Bertrand, Rodrigo Possamai Bastos, Laurent Fesquet:
  A Practical Framework for Specification, Verification, and Design of Self-Timed Pipelines. ASYNC 2017: 65-72
• 
  Montek Singh, Pintian Zhang, Andrew Vitkus, Ketan Mayer-Patel, Leandra Vicci:
  A Frameless Imaging Sensor with Asynchronous Pixels: An Architectural Evaluation. ASYNC 2017: 110-117
• 
  Ghaith Tarawneh, Matthias Függer, Christoph Lenzen:
  Metastability Tolerant Computing. ASYNC 2017: 25-32
• 
  Maxwell Waugaman, William Koven:
  Sharp - A Resilient Asynchronous Template. ASYNC 2017: 83-84
• 
  23rd IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2017, San Diego, CA, USA, May 21-24, 2017. IEEE Computer Society 2017, ISBN 978-1-5386-2749-5 [contents]