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ORCIDAbdelkarim Cherkaoui
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2020 – today
- 2021
[j3]Jérémy Belot
, Abdelkarim Cherkaoui, Raphaël Laurent, Laurent Fesquet:
An Area- and Power-Efficient Stochastic Number Generator for Bayesian Sensor Fusion Circuits. IEEE Des. Test 38(6): 69-77 (2021)- [c17]Jérémy Belot, Abdelkarim Cherkaoui, Raphaël Laurent, Laurent Fesquet:
An Energy Efficient Multi-Rail Architecture for Stochastic Computing: A Bayesian Sensor Fusion Case Study. ICECS 2021: 1-5 - 2020
- [c16]Grégoire Gimenez, Abdelkarim Cherkaoui, Laurent Fesquet:
A Self-Timed Ring based PUF. ASYNC 2020: 69-77
2010 – 2019
- 2018
- [j2]Cédric Marchand, Lilian Bossuet, Ugo Mureddu, Nathalie Bochard, Abdelkarim Cherkaoui, Viktor Fischer:
Implementation and Characterization of a Physical Unclonable Function for IoT: A Case Study With the TERO-PUF. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(1): 97-109 (2018) - [c15]Gregoire Gimenez, Abdelkarim Cherkaoui, Guillaume Cogniard, Laurent Fesquet:
Static Timing Analysis of Asynchronous Bundled-Data Circuits. ASYNC 2018: 110-118 - [c14]Mathieu Coustans, Abdelkarim Cherkaoui, Laurent Fesquet, Christian Terrier, Stephanie Salgado, Thomas Eberhardt, Maher Kayal:
Subthreshold logic for low-area and energy efficient true random number generator. COOL CHIPS 2018: 1-3 - [c13]Oussama Elissati, Assia El-Hadbi, Abdelkarim Cherkaoui, Sébastien Rieubon, Laurent Fesquet:
Low Phase-Noise CMOS Quadrature Oscillator based on (N × 4)-stage Self-Timed Ring. DCIS 2018: 1-5 - 2017
- [c12]Jean Simatic, Abdelkarim Cherkaoui, François Bertrand, Rodrigo Possamai Bastos, Laurent Fesquet:
A Practical Framework for Specification, Verification, and Design of Self-Timed Pipelines. ASYNC 2017: 65-72 - [c11]François Bertrand, Abdelkarim Cherkaoui, Jean Simatic, Anthony Maure, Laurent Fesquet:
CAR: On the highway towards de-synchronization. ICECS 2017: 339-343 - [c10]Gregoire Gimenez, Abdelkarim Cherkaoui, Raphael Frisch, Laurent Fesquet:
Self-timed Ring based True Random Number Generator: Threat model and countermeasures. IVSW 2017: 31-38 - [c9]Assia El-Hadbi, Abdelkarim Cherkaoui, Oussama Elissati, Jean Simatic, Laurent Fesquet:
On-the-fly and sub-gate-delay resolution TDC based on self-timed ring: A proof of concept. NEWCAS 2017: 305-308 - 2016
- [j1]Abdelkarim Cherkaoui, Lilian Bossuet, Cédric Marchand:
Design, Evaluation, and Optimization of Physical Unclonable Functions Based on Transient Effect Ring Oscillators. IEEE Trans. Inf. Forensics Secur. 11(6): 1291-1305 (2016) - [c8]Cédric Marchand, Lilian Bossuet, Abdelkarim Cherkaoui:
Enhanced TERO-PUF Implementations and Characterization on FPGAs (Abstract Only). FPGA 2016: 282 - [c7]Cédric Marchand, Lilian Bossuet, Abdelkarim Cherkaoui:
Design and Characterization of the TERO-PUF on SRAM FPGAs. ISVLSI 2016: 134-139 - [c6]Jean Simatic, Abdelkarim Cherkaoui, Rodrigo Possamai Bastos, Laurent Fesquet:
New asynchronous protocols for enhancing area and throughput in bundled-data pipelines. SBCCI 2016: 1-6 - 2014
- [c5]Laurent Fesquet, Abdelkarim Cherkaoui, Oussama Elissati:
Self-timed rings as low-phase noise programmable oscillators. NEWCAS 2014: 409-412 - [c4]Abdelkarim Cherkaoui, Lilian Bossuet, Ludwig Seitz, Göran Selander, Ravishankar Borgaonkar:
New paradigms for access control in constrained environments. ReCoSoC 2014: 1-4 - 2013
- [c3]Abdelkarim Cherkaoui, Viktor Fischer, Alain Aubert, Laurent Fesquet:
A Self-Timed Ring Based True Random Number Generator. ASYNC 2013: 99-106 - [c2]Abdelkarim Cherkaoui, Viktor Fischer, Laurent Fesquet, Alain Aubert:
A Very High Speed True Random Number Generator with Entropy Assessment. CHES 2013: 179-196 - 2012
- [c1]Abdelkarim Cherkaoui, Viktor Fischer, Alain Aubert, Laurent Fesquet:
Comparison of Self-Timed Ring and Inverter Ring Oscillators as entropy sources in FPGAs. DATE 2012: 1325-1330
Coauthor Index
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