default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID21st COOL CHIPS 2018: Yokohama, Japan
- 2018 IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS 2018, Yokohama, Japan, April 18-20, 2018. IEEE Computer Society 2018, ISBN 978-1-5386-6103-1
- Ryosuke Kazami, Hayate Okuhara, Hideharu Amano:
Design automation methodology of a critical path monitor for adaptive voltage controls. 1-3 - Vinod Pangracious
, Ranjitha Dash, Ashok Kumar Turuk:
3D-cool: Design and development of adaptive thermal-aware three-dimensional NoC-based multiprocessor chip. 1-3 - Koji Inoue, Takuya Araki, Takumi Maruyama, Pritish Narayanan, Takashi Oshima, Martin Schulz:
Panel discussions: "Challenges to the scaling limits: How can we achieve sustainable power-performance improvements?". 1-2 - Andrawes Al Bahou, Geethan Karunaratne, Renzo Andri, Lukas Cavigelli, Luca Benini:
XNORBIN: A 95 TOp/s/W hardware accelerator for binary convolutional neural networks. 1-3 - Dionysios Diamantopoulos, Heiner Giefers, Christoph Hagleitner:
ecTALK: Energy efficient coherent transprecision accelerators - The bidirectional long short-term memory neural network case. 1-3 - Takahiro Ichikura, Ryusuke Yamano, Yuma Kikutani, Renyuan Zhang, Yasuhiko Nakashima:
EMAXVR: A programmable accelerator employing near ALU utilization to DSA. 1-3 - Ken Tanabe, Hiroshi Kubota, Akihide Sai, Nobu Matsumoto:
Data selection and de-noising based on reliability for long-range and high-pixel resolution LiDAR. 1-3 - Noriyuki Uetake, Renyuan Zhang, Takashi Nakada, Yasuhiko Nakashima:
A programmable analog calculation unit for vector computations. 1-3 - Mathieu Coustans, Abdelkarim Cherkaoui, Laurent Fesquet, Christian Terrier, Stephanie Salgado, Thomas Eberhardt, Maher Kayal:
Subthreshold logic for low-area and energy efficient true random number generator. 1-3 - Masayuki Sato, Zehua Li, Ryusuke Egawa, Hiroaki Kobayashi:
An energy-aware set-level refreshing mechanism for eDRAM last-level caches. 1-3 - Tetsuya Odajima, Yuetsu Kodama, Mitsuhisa Sato:
Power performance analysis of ARM scalable vector extension. 1-3 - Kesami Hagiwara, Tomoichi Hayashi, Shumpei Kawasaki, Fumio Arakawa, Oleg Endo, Hayato Nomura, Akira Tsukamoto, Duong Nguyen, Binh Nguyen, Anh Tran, Hoan Hyunh, Ikuo Kudoh, Cong-Kha Pham:
A two-stage-pipeline CPU of SH-2 architecture implemented on FPGA and SoC for IoT, edge AI and robotic applications. 1-3
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-02-24 21:37 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
