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Huimei Cheng

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Journal Articles

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2022
[j6]
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  - journals/tcad/ChengLGB22
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  - https://dblp.org/rec/journals/tcad/ChengLGB22
Huimei Cheng, Xi Li, Yichen Gu, Peter A. Beerel:
Converting Flip-Flop to Clock-Gated 3-Phase Latch-Based Designs Using Graph-Based Retiming. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(4): 979-992 (2022)
2020
[j5]
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  - journals/tcas/AketiGCMB20
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Sai Aparna Aketi, Smriti Gupta, Huimei Cheng, Joycee Mekie, Peter A. Beerel:
SERAD: Soft Error Resilient Asynchronous Design Using a Bundled Data Protocol. IEEE Trans. Circuits Syst. I Fundam. Theory Appl. 67-I(5): 1667-1677 (2020)
2019
[j4]
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  - journals/iet-cdt/ZhangLCZDB19
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Yang Zhang, Ji Li, Huimei Cheng, Haipeng Zha, Jeffrey Draper, Peter A. Beerel:
Yield modelling and analysis of bundled data and ring-oscillator based designs. IET Comput. Digit. Tech. 13(3): 262-272 (2019)
[j3]
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  - journals/mcs/ChengHZ19
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Huimei Cheng, Huan Huang, Kai Zhang:
Study on the influence of bus front-end intrusion-free distance to the bus moving characteristics. Math. Comput. Simul. 155: 303-313 (2019)
[j2]
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  - journals/tcad/ChengWZHB19
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Huimei Cheng, Hsiao-Lun Wang, Minghe Zhang, Dylan Hand, Peter A. Beerel:
Automatic Retiming of Two-Phase Latch-Based Resilient Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(7): 1305-1316 (2019)
2018
[j1]
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  - journals/tcad/HuangCCB18
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Hsin-Ho Huang, Huimei Cheng, Chris Chu, Peter A. Beerel:
Area Optimization of Timing Resilient Designs Using Resynthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(6): 1197-1210 (2018)

Conference and Workshop Papers

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2020
[c5]
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  - conf/date/ChengLGB20
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Huimei Cheng, Xi Li, Yichen Gu, Peter A. Beerel:
Saving Power by Converting Flip-Flop to 3-Phase Latch-Based Designs. DATE 2020: 574-579
2018
[c4]
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  - conf/async/0014CCFALB18
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Yang Zhang, Huimei Cheng, Dake Chen, Huayu Fu, Shikhanshu Agarwal, Mark Lin, Peter A. Beerel:
Challenges in Building an Open-Source Flow from RTL to Bundled-Data Design. ASYNC 2018: 26-27
2017
[c3]
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  - conf/async/0014ZSCB17
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Yang Zhang, Haipeng Zha, Vaishnavi Sahir, Huimei Cheng, Peter A. Beerel:
Test Margin and Yield in Bundled Data and Ring-Oscillator Based Designs. ASYNC 2017: 85-93
[c2]
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  - conf/glvlsi/ChengLDNW17
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Huimei Cheng, Ji Li, Jeffrey T. Draper, Shahin Nazarian, Yanzhi Wang:
Deadline-Aware Joint Optimization of Sleep Transistor and Supply Voltage for FinFET Based Embedded Systems. ACM Great Lakes Symposium on VLSI 2017: 427-430
2016
[c1]
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  - conf/dac/HuangCCB16
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Hsin-Ho Huang, Huimei Cheng, Chris C. N. Chu, Peter A. Beerel:
Area optimization of resilient designs guided by a mixed integer geometric program. DAC 2016: 130:1-130:6

Informal and Other Publications

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2020
[i2]
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  - journals/corr/abs-2001-04039
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Sai Aparna Aketi, Smriti Gupta, Huimei Cheng, Joycee Mekie, Peter A. Beerel:
SERAD: Soft Error Resilient Asynchronous Design using a Bundled Data Protocol. CoRR abs/2001.04039 (2020)
2019
[i1]
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  - journals/corr/abs-1906-10666
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Huimei Cheng, Yichen Gu, Peter A. Beerel:
Automatic Conversion from Flip-flop to 3-phase Latch-based Designs. CoRR abs/1906.10666 (2019)

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