- Kaushik Roy, Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand
:
Leakage Current in Deep-Submicron CMOS Circuits. J. Circuits Syst. Comput. 11(6): 575-600 (2002) - Abdhesh K. Singh, Raj Senani:
A New Four-CC-Based Configuration for Realizing a Voltage-Mode Biquad Filter. J. Circuits Syst. Comput. 11(3): 213-218 (2002) - Paul-Peter Sotiriadis, Anantha P. Chandrakasan:
Power Estimation and Power Optimal Communication in Deep Submicron Buses: Analytical Models and Statistical Measures. J. Circuits Syst. Comput. 11(6): 637-658 (2002) - Thambipillai Srikanthan, Bimal Gisuthan:
Optimizing Scaling Factor Computations in Flat Cordic. J. Circuits Syst. Comput. 11(1): 17-34 (2002) - Ankur Srivastava, Eren Kursun, Majid Sarrafzadeh:
Predictability in RT-Level Designs. J. Circuits Syst. Comput. 11(4): 323-332 (2002) - Shaohua Tang:
Correlative Message Group Digital Signature and Its Application to E-Commerce. J. Circuits Syst. Comput. 11(1): 73-80 (2002) - Frank Vahid, Tony Givargis, Susan Cotterell:
Power Estimator Development for Embedded System Memory Tuning. J. Circuits Syst. Comput. 11(5): 459-476 (2002) - Dimitrios Velenis, Kevin T. Tang, Ivan S. Kourtev, Victor Adler, Franklin Baez, Eby G. Friedman:
Demonstration of Speed and Power Enhancements on an Industrial Circuit Through Application of Clock Skew Scheduling. J. Circuits Syst. Comput. 11(3): 231-246 (2002) - H. H. Wong, K. T. Lau:
Low Power 16 x 16 Bit Multiplier Design Using PAL-2N Logic Family. J. Circuits Syst. Comput. 11(2): 155-164 (2002) - Yi-Jong Yeh, Sy-Yen Kuo:
An Optimization-Based Multiple-Voltage Scaling Technique for Low-Power CMOS Digital Design. J. Circuits Syst. Comput. 11(4): 365-376 (2002) - Saif Zahir, Rabab K. Ward:
A New Edge Preserving Binary Images Resizing Technique. J. Circuits Syst. Comput. 11(3): 247-258 (2002) - Yikui Zhang, Etsuro Hayahara, Satoshi Hirano, Naohito Sakakibara:
An Optimal Design Consideration for Higher-Order Delta-Sigma AD Converter. J. Circuits Syst. Comput. 11(2): 103-114 (2002) - Hongtao Zhang, Huiyun Wang, Wai-Kai Chen:
Oversampled Chaotic Binary Sequences with Good Security. J. Circuits Syst. Comput. 11(2): 173-186 (2002) - Yi-Sheng Zhu, Wai-Kai Chen:
Short-Step Butterworth Impedance Transformers. J. Circuits Syst. Comput. 11(2): 165-172 (2002)
